Leading-Edge Thin-Layer MOSFET Potential Modeling Toward Short-Channel Effect Suppression and Device Optimization

Abstract

A novel compact model has been developed, which considers the origin of the short-channel effect (SCE) on the basis of the potential distribution along the channel. Thus an enlargement of the insight into SCE suppression in advanced thin-layer MOSFETs is enabled. The model is extended to include the diffusion region resistance effects caused by the drain-side doping by applying the methodology of the industry-standard high-voltage MOSFET model HiSIM_HV. Usage for studying possible device optimizations revealed that clear improvements in the subthreshold characteristics due to suppression of SCEs can be achieved by slightly increasing the drain-side diffusion resistance. Disadvantageous effects on the device and circuit performances were found to be negligible.INDEX TERMS Short channel transistor, compact modeling, double-gate MOSFET, subthreshold characteristics.

Compact Modeling of Multi-Gate MOSFETs for High-Power Applications

“…ϕ0+Vds is the potential at drain contact. The developed model has been extended to include both effects [14]. To understand the resistance effect of the drain diffusion region, the potential distribution along a highly resistive drain region at high applied gate and drain biases is schematically depicted in Fig.…”

“…For the expansion of the depletion region, mainly observed during subthreshold operation of short-channel transistors, the potential difference Vdi is modulated by the potential drop along the depletion region formed at the drain side (see Fig. 6) [14], [26] [27] di dp biDrain biSource Drain…”

“…However, it is still hard to reduce the short-channel effects sufficiently, even with an extremely thin channel layer [10]. Compact modeling for the thin-layer devices has been mostly done through the study of physics-based device simulations [11]- [14]. We have developed a consistently potential-based compact model for the short-channel effects in such leading-edge thin-layer MOSFETs [1], and demonstrated that the origin of the short-channel effects is the leakage current This paragraph of the first footnote will contain the date on which you submitted your paper for review.…”

“…In this context, it has further been demonstrated that a small reduction of the drain-doping concentration can suppress the short-channel effects quite drastically, while causing a small increase in the drainresistance effect and in the power loss at the same time. Fortunately, a favorable compromise between short-channeleffect reduction and power-loss increase can be achieved [14].…”

Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs

“…Soumajit Ghosh, M. Miura-Mattausch, T. Iizuka and H. J. Mattausch are with the HiSIM Research Center, Hiroshima University, Higashihiroshima 739-8530, Japan (e-mail: ghoshsoumajit@hiroshima-u.ac.jp; mmm@hiroshimau.ac.jp; iizuka@hiroshima-u.ac.jp; hjm@hiroshima-u.ac.jp) to reduce dynamic power loss, as it has a quadratic relationship with the switching loss [14][15]. However, scaling down the supply voltage weakens the front-gate control over the channel, especially for short-channel-length devices, due to the lateralfield dominance, produced by the source/drain junction depletion extension [16][17][18]. This degrades the subthreshold slope.…”