Latest results on 1200 V 4H-SiC CIMOSFETs with R&lt;inf&gt;sp, on&lt;/inf&gt; of 3.9 m&amp;#x03A9;&amp;#x00B7;cm&lt;sup&gt;2&lt;/sup&gt; at 150&amp;#x00B0;C

Zhang, Qingchun Jon; Wang, Gangyao; Doan, Huy; Ryu, Sei‐Hyung; Hull, Brett; Young, Jonathan; Allen, Scott T.; Palmour, John W.

doi:10.1109/ispsd.2015.7123396

Cited by 17 publications

(15 citation statements)

References 3 publications

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“…The area under the active channel is reduced, which enhances the switching performance by reducing the gate-drain capacitance. Central implant MOSFET (CI MOSFET) is another type of structure demonstrated by Wolfspeed; it exhibits lower C GD and Q GD [154]. In power inverter applications, to reduce the SiC Chip area, SiC MOSFETs are used with free-wheeling diodes (FWD), namely, parasitic body PiN diodes.…”

Section: Planar and Trench Mosfetsmentioning

confidence: 99%

Review of Silicon Carbide Processing for Power MOSFET

et al. 2022

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Owing to the superior properties of silicon carbide (SiC), such as higher breakdown voltage, higher thermal conductivity, higher operating frequency, higher operating temperature, and higher saturation drift velocity, SiC has attracted much attention from researchers and the industry for decades. With the advances in material science and processing technology, many power applications such as new smart energy vehicles, power converters, inverters, and power supplies are being realized using SiC power devices. In particular, SiC MOSFETs are generally chosen to be used as a power device due to their ability to achieve lower on-resistance, reduced switching losses, and high switching speeds than the silicon counterpart and have been commercialized extensively in recent years. A general review of the critical processing steps for manufacturing SiC MOSFETs, types of SiC MOSFETs, and power applications based on SiC power devices are covered in this paper. Additionally, the reliability issues of SiC power MOSFET are also briefly summarized.

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Section: Planar and Trench Mosfetsmentioning

confidence: 99%

Review of Silicon Carbide Processing for Power MOSFET

et al. 2022

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“…JFET,sp JFET jP cell ρ = a xW R [3] where ρJFET is the resistivity of the JFET region, xJP is the depth of the P + shielding region, and 'a' is the effective width for vertical current flow through the JFET region. For the model without accounting for straggle LSP+, the value for 'a' is given by [24]:…”

Section: On-state Characteristicsmentioning

confidence: 99%

Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic Parameters

Agarwal

Baliga

2022

IEEE J. Electron Devices Soc.

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Significant impact of the ion-implant straggle of the P + shielding region on the static and dynamic characteristics of 1.2 kV 4H-SiC power MOSFETs is demonstrated in this paper by using analytical and TCAD modelling. The P + region ion-implant straggle not only reduces the JFET width but increases the channel length. This combination is shown to displace a SiC power MOSFET structure optimized without ion-implant straggle away from the optimum JFET width required to achieve the lowest specific on-resistance, resulting in an increase in the specific on-resistance by a factor of 2-3x for the typically used JFET width of 0.7 m. The theoretical analysis is supported by data measured on 1.2 kV SiC power MOSFETs fabricated with channel lengths of 0.3 and 0.5 m using both accumulation and inversion mode channels. The presence of the P + shielding region ion-implant straggle is shown to: (a) increase specific onresistance by 15-30%; (b) suppress short-channel effects; (c) reduce electric field in the gate oxide; (d) reduce the transconductance; (e) reduce saturated drain current; and (f) significantly reduce the gate-drain capacitance and gate charge. Impact of P + shielding region lateral straggle on device cell optimization is an important contribution of this paper.

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“…Wolfspeed reported a Central Implant MOSFET (CIMOSFET) to reduce both the C gd and R on [8], but an extra implantation mask step is required. A Buffered Gate MOS (BG-MOS) structure was recently proposed to reduce C gd and the gate oxide electric field [9], as shown in Figure 1b.…”

Section: Introductionmentioning

confidence: 99%

1.2 kV 4H‐SiC planar power MOSFETs with a low‐K dielectric in central gate

Liu

et al. 2022

IET Circuits, Devices & Syst

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A 1.2 kV 4H-SiC planar power MOSFET with a low-K dielectric in central gate (LK-MOS) is proposed in this paper. The LK-MOS features a P+ shielding region and a thick low-K dielectric layer under the central gate. The insulation layer capacitance is reduced by the thick low-K dielectric, while the depletion layer capacitance is decreased due to the reduced gate-to-drain overlap. The LK-MOS is demonstrated to have 97.8%, 70.6%, and 52.2% lower HF-FOM (R on � C gd ), and 98.9%, 97.4%, and 69.4% lower HF-FOM (R on � Q gd ), when compared with that of the conventional MOSFET (C-MOS), Buffered-Gate MOSFET (BG-MOS) and Thick Central Oxide MOSFET (TCOX-MOS), respectively. Besides, the LK-MOS can also have 16.8%, 5.9% lower C gs , and 19.9%, 12.4% lower Q gs compared with that of BG-MOS and TCOX-MOS.

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Latest results on 1200 V 4H-SiC CIMOSFETs with R<inf>sp, on</inf> of 3.9 mΩ·cm<sup>2</sup> at 150°C

Cited by 17 publications

References 3 publications

Review of Silicon Carbide Processing for Power MOSFET

Review of Silicon Carbide Processing for Power MOSFET

Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic Parameters

1.2 kV 4H‐SiC planar power MOSFETs with a low‐K dielectric in central gate

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