Latch Susceptibility to Transient Faults and New Hardening Approach

Omaña, M.; Rossi, Daniele; Metra, C.

doi:10.1109/tc.2007.1070

Cited by 125 publications

(90 citation statements)

References 31 publications

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“…Among sequential elements, latch is the most fragile element to soft error since its latching window is much longer than other register elements [8]. Recently, there are many soft error mitigation latch designs have been proposed [4,5,6,7,8,9]. These designs can be classified into the node strengthen type and the soft-error isolation type.…”

Section: Introductionmentioning

confidence: 99%

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Robust C-element design for soft-error mitigation

Wey

Peng

et al. 2015

IEICE Electron. Express

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C-element is a widely used component in soft-error tolerant designs to construct a robust soft-tolerant mechanism; however, C-element itself is not a robust device. In this paper, we proposed a robust C-element design by employing two transistors operating in saturation region parallel connected with C-element upper pMOS and lower nMOS to enhance its softerror tolerance. By utilizing the proposed C-element in the prior-art isolated latch designs, the maximum soft error tolerance can be improved by 25.87% as compared with conventional C-element.

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Section: Introductionmentioning

confidence: 99%

“…These designs can be classified into the node strengthen type and the soft-error isolation type. Usually, the soft-error isolation designs [6,7,8,9] can provide more superior soft error resilience by masking the propagation of soft error with a key component, C-element. C-element is supposed to be soft error free.…”

Section: Introductionmentioning

confidence: 99%

Robust C-element design for soft-error mitigation

Wey

Peng

et al. 2015

IEICE Electron. Express

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“…Soft errors (SEs) would be the fifth major problem following the speed, chip area, power consumption, and yield in large-scale integration (LSI) design [2]. Around 90% of the SEinfluenced circuits were memory circuits in the early years, and most of SE issues in memory elements have been discussed and overcome [3]. However, SE issues still exist in arithmetic circuits or digital signal processing (DSP) systems.…”

Section: Introductionmentioning

confidence: 99%

Reliable and low error dual modular redundancy FIR filter with wide protection window

Wey

Peng

Chou

et al. 2014

IEICE Electron. Express

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“…The instant-on operation is still possible and is evoked when following the loss of power, data stored in the resistive element is transferred also to the SRAM core upon the availability of power. Moreover, as for the occurrence of an SEU, the node of critical charge is considered [73,74,75]; as shown in a later section (and consistent with other works on NVSRAMs [69]), this node is DN. Once a SEU occurs, it results in a state change at DN, thus also causing D to change accordingly (due to the cross-coupled inverter scheme of the SRAM core).…”

Section: Pmc-based Nvsram With Concurrent Seu Detection and Correctionmentioning

confidence: 73%

“…The sensitivity of SRAM to radiation is quantified by the critical charge parameter, Q crit , as the least amount of charge required to change the state of the cell [73,82]. Table 30 shows the critical charge of the 7T1P cell for the three nodes D, DN and DP for '0' and '1' as data stored in the cell.…”

Section: Single Event Upset (Seu) Tolerancementioning

confidence: 99%

Design and modeling of nonvolatile memories by resistive switching elements

Junsangsri¹

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With the continued scaling in the nano ranges, the technology roadmap predicted by Moore's Law is becoming difficult to meet. So-called emerging technologies have been widely reported to supersede or complement CMOS. This type of design style is commonly referred to as "hybrid" because it exploits different characteristics of emerging technologies. This is very attractive for memories in which the modular (cell-based) organization of these systems is well suited to new technologies and innovative paradigms for design. This research presents new hybrid memory design which employ emerging technologies; such as memristor, phase change memory (PCM), programmable metallization cell (PMC), and racetrack memory (RM); and CMOS. By introduced new HSPICE macromodel of these emerging technologies and their memory applications such as the nonvolatile memory cell, CAM, TCAM, NVSRAM, and crossbar array, hybrid nonvolatile memory cells are generated. With its nonvolatile storage element, fast switching time, low power consumption, and good scalability, the hybrid memory cell of emerging technologies and CMOS would be one of the most promising candidates for the next generation of the nonvolatile memory.iii ACKNOWLEDGEMENTS

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Latch Susceptibility to Transient Faults and New Hardening Approach

Cited by 125 publications

References 31 publications

Robust C-element design for soft-error mitigation

Robust C-element design for soft-error mitigation

Reliable and low error dual modular redundancy FIR filter with wide protection window

Design and modeling of nonvolatile memories by resistive switching elements

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