Larrabee: A Many-Core x86 Architecture for Visual Computing

Seiler, Larry; Carmean, Doug; Sprangle, Eric; Forsyth, Tom; Dubey, Pradeep; Junkins, Stephen; Lake, Adam; Cavin, Ralph K.; Espasa, Roger; Grochowski, Ed; Juan, Toni; Abrash, Michael; Sugerman, Jeremy; Hanrahan, Pat

doi:10.1109/mm.2009.9

Cited by 257 publications

(245 citation statements)

References 8 publications

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“…Intel [32] graphics processors coming. The comparisons herein must of course be re-evaluated with each new instruction set and new silicon implementation, but we believe that the general trend stands on our side.…”

Section: Discussionmentioning

confidence: 99%

SSE Implementation of Multivariate PKCs on Modern x86 CPUs

Chen

et al. 2009

Lecture Notes in Computer Science

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Abstract. Multivariate Public Key Cryptosystems (MPKCs) are often touted as future-proofing against Quantum Computers. It also has been known for efficiency compared to "traditional" alternatives. However, this advantage seems to erode with the increase of arithmetic resources in modern CPUs and improved algorithms, especially with respect to Elliptic Curve Cryptography (ECC). In this paper, we show that hardware advances do not just favor ECC. Modern commodity CPUs also have many small integer arithmetic/logic resources, embodied by SSE2 or other vector instruction sets, that are useful for MPKCs. In particular, Intel's SSSE3 instructions can speed up both public and private maps over prior software implementations of Rainbow-type systems up to 4×. Furthermore, MPKCs over fields of relatively small odd prime characteristics can exploit SSE2 instructions, supported by most modern 64-bit Intel and AMD CPUs. For example, Rainbow over F31 can be up to 2× faster than prior implementations of similarly-sized systems over F16. Here a key advance is in using Wiedemann (as opposed to Gauss) solvers to invert the small linear systems in the central maps. We explain the techniques and design choices in implementing our chosen MPKC instances over fields such as F31, F16 and F256. We believe that our results can easily carry over to modern FPGAs, which often contain a large number of small multipliers, usable by odd-field MPKCs.

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Section: Discussionmentioning

confidence: 99%

SSE Implementation of Multivariate PKCs on Modern x86 CPUs

Chen

et al. 2009

Lecture Notes in Computer Science

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“…Some of the more recent such research aims to effectively employ powerful dedicated and specialized co-processors like graphic cards. Notable VM designs in this direction are the CellVM [15], [30] for the Cell Broadband Engine, a VM with a distributed Java heap on a homogeneous TILE-64 system [28]; an extension of the JikesVM to detect and offload loops on CUDA devices [12]; and VMs for Intel's Larrabee GPGPU architecture [22]. Most of these designs are specific to VMs for Java-like languages which are based on a shared-memory concurrent programming model.…”

Section: Vm Support For High-level Concurrencymentioning

confidence: 99%

RELEASE: A High-Level Paradigm for Reliable Large-Scale Server Software

Boudeville

Cesarini²,

Chechina

et al. 2013

Lecture Notes in Computer Science

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Abstract. Erlang provides a fault-tolerant, reliable model for building concurrent, distributed system based on functional programming. In the RELEASE project the Erlang model is extended to Scalable Distributed Erlang -SD Erlang -supporting general-purpose computation in massively multicore systems. This paper outlines the RELEASE proposal, and indicates the progress of the project in its first six months.

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“…Upcoming architectures [5] will also feature gather (scatter) operations that can load (store) from (to) a base address using a vector of (possibly non-consecutive) offsets. On architectures without scatter/gather instructions such non-consecutive accesses are very slow.…”

Section: Simd Instruction Setsmentioning

confidence: 99%

Whole-function vectorization

Karrenberg

Hack

2011

International Symposium on Code Generation and Optimization (CGO 2011)

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Abstract-Data-parallel programming languages are an important component in today's parallel computing landscape. Among those are domain-specific languages like shading languages in graphics (HLSL, GLSL, RenderMan, etc.) and "general-purpose" languages like CUDA or OpenCL. Current implementations of those languages on CPUs solely rely on multi-threading to implement parallelism and ignore the additional intra-core parallelism provided by the SIMD instruction set of those processors (like Intel's SSE and the upcoming AVX or Larrabee instruction sets).In this paper, we discuss several aspects of implementing dataparallel languages on machines with SIMD instruction sets. Our main contribution is a language-and platform-independent code transformation that performs whole-function vectorization on low-level intermediate code given by a control flow graph in SSA form.We evaluate our technique in two scenarios: First, incorporated in a compiler for a domain-specific language used in realtime ray tracing. Second, in a stand-alone OpenCL driver. We observe average speedup factors of 3.9 for the ray tracer and factors between 0.6 and 5.2 for different OpenCL kernels.

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Larrabee: A Many-Core x86 Architecture for Visual Computing

Cited by 257 publications

References 8 publications

SSE Implementation of Multivariate PKCs on Modern x86 CPUs

SSE Implementation of Multivariate PKCs on Modern x86 CPUs

RELEASE: A High-Level Paradigm for Reliable Large-Scale Server Software

Whole-function vectorization

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