(Invited) Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

Abstract

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

In Situ HCl Etching of InP in Shallow-Trench-Isolated Structures

“…Although smooth and planar, at closer inspection the InP recessed surface shows the presence of shallow grooves running perpendicularly to the trenches direction. From previous experiments, we know that these features are related to either anti-phase domain boundaries (APB) or stacking faults, originating at the Ge/InP interface and traveling to the InP surface 4 as observed on Fig. 6d.…”

“…1,2 One of the possible fabrication processes to integrate III-V materials on Si substrates is the selective area growth (SAG) in shallow trench isolation (STI) structures. 3,4 A significant advantage of SAG in submicrometer trenches is the extended defect necking effect, also known as aspect-ratio-trapping (ART) technique. 5 If the aspect ratio of the trench is >2, the dislocations, which form as a consequence of the lattice mismatch between InP and Si, stop at the sidewalls, leaving a low defect density material in the upper part of the trench.…”

In Situ HCl Etching of InP in Shallow-Trench-Isolated Structures

“…Although smooth and planar, at closer inspection the InP recessed surface shows the presence of shallow grooves running perpendicularly to the trenches direction. From previous experiments, we know that these features are related to either anti-phase domain boundaries (APB) or stacking faults, originating at the Ge/InP interface and travelling to the InP surface [4] as observed on Fig. 6(d).…”

“…One of the possible fabrication processes to integrate III-V materials on Si substrates is the selective area growth (SAG) in shallow trench isolation (STI) structures [3,4]. A significant advantage of SAG in sub-micrometer trenches is the extended defect necking effect, also known as aspect-ratio-trapping (ART) technique [5].…”

“…High mobility III-V and Ge channel materials on Si substrates have been demonstrated to be strong candidates to future high performance and low power CMOS devices below 12 nm node [1,2]. One of the possible fabrication processes to integrate III-V materials on Si substrates is the selective area growth (SAG) in shallow trench isolation (STI) structures [3,4]. A significant advantage of SAG in sub-micrometer trenches is the extended defect necking effect, also known as aspect-ratio-trapping (ART) technique [5].…”