(Invited) Challenges for Etch Technology and the Integration of New Channel Materials Beyond 7 nm

Abstract

Integration of new channel materials in current semiconductor manufacturing scheme would represent a leap advance in CMOS technology. Processing of new channel materials (III-V's, Ge and SiGe) via dry etch poses significant challenges. Dry (plasma) etch can be used to pattern channel materials after they are deposited using an epitaxial process; alternatively channels maybe inserted into bounded (for example an oxide) recesses (for example silicon) fabricated using etch technologies already developed for FinFET and SAQP applications. With dry etch technology there is the everpresent worry of damage. Atomic later etching (ALE) is an emerging viable option for damage free etch. This presentation will show how conventional and advanced plasma etch technologies provide a path for logic manufacture beyond 7 nm with a realistic picture of the trade-offs that must be handled for introduction of III-V materials, Ge or SiGe.