The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915 • C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO 2 and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES. Monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal-oxide semiconductor (CMOS) enables advanced circuits with increased performance and functionality and promotes system-level miniaturization. The Silicon on Lattice Engineered Substrate (SOLES) platform is a Si wafer with embedded III-V template layer that has been developed for III-V/Si integration and is illustrated in Fig. 1. 1,2 A silicon-on-insulator (SOI) layer on top provides the high quality substrate necessary for CMOS device processing whereas the III-V template acts as a seed layer for epitaxial III-V device growth. This III-V template layer is accessed by etching windows through the top Si and buried insulator layers. The SOLES substrate structure is designed to add functionality to a CMOS platform while maintaining compatibility with Si processing infrastructure. Exposure to the III-V template layer is avoided until the CMOS process sequence is complete and the III-V device epitaxy and processing can be treated in a similar manner to backend metal processing.