Investigating the impact of NBTI on different power saving cache strategies

Ricketts,; Singh, Varsha; Ramakrishnan,; Vijaykrishnan,; Pradhan,

doi:10.1109/date.2010.5457137

Cited by 35 publications

(41 citation statements)

References 17 publications

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“…It can be obviously seen that the distributions are leaning to the left. It is because in data cache memory, logic '0' is more dominant than logic '1' [38]. In fact, memory is typically initialized to all '0's when allocated.…”

Section: Performance-reliability Analysis For Different Cache Configumentioning

confidence: 99%

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

Liu¹,

Chen²,

Milor³

2018

Dependability Engineering

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The majority of transistors in a modern microprocessor are used to implement static random access memories (SRAM). Therefore, it is important to analyze the reliability of SRAM blocks. During the SRAM design, it is important to build in design margins to achieve an adequate lifetime. The two main wearout mechanisms that increase a transistor's threshold voltage are bias temperature instability (BTI) and hot carrier injections (HCI). BTI and HCI can degrade transistors' driving strength and further weaken circuit performance. In a microprocessor, first-level (L1) caches are frequently accessed, which make it especially vulnerable to BTI and HCI. In this chapter, the cache lifetimes due to BTI and HCI are studied for different cache configurations, namely, cache size, associativity, cache line size, and replacement algorithm. To give a case study, the failure probability (reliability) and the hit rate (performance) of the L1 cache in a LEON3 microprocessor are analyzed, while the microprocessor is running a set of benchmarks. Essential insights can be provided from our results to give better performance-reliability tradeoffs for cache designers.

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Section: Performance-reliability Analysis For Different Cache Configumentioning

confidence: 99%

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

Liu¹,

Chen²,

Milor³

2018

Dependability Engineering

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“…However, as demonstrated in [7], the returns on dynamic voltage scaling diminish due to the "front-loaded" nature of degradation and it cannot be used to extend the lifetime of the processor. Since the device is only under stress when a negative-bias (V GS = −V dd | ′ 0 ′ ) is applied, the duty cycle (β) is an important parameter that can influence ∆V th significantly [8]. Figure 1 shows the impact of duty cycle variation on the ∆V th for a 32nm PTM PMOS device operating at 85…”

Section: Background and Motivationmentioning

confidence: 99%

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches

Ganapathy

Canal

González

et al. 2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Abstract-Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical variations of process parameters, it can potentially render systems dysfunctional in certain scenarios. Data caches suffer the most from such phenomenon because of the unbalanced duty cycle ratio of SRAM cells and maximum intrinsic susceptibility to process variations. In this paper, we propose a novel NBTI-aware technique, invertRead-Modify-Write (iRMW) that can improve the functional yield of the data cache significantly over its lifetime. Using architecture-level benchmarks, we first analyse the impact of activity factor and workload variation on NBTI-induced failures in data caches. iRMW is then used as a means to balance the duty cycle by alternating between recovery and stress cycle upon successive read accesses to the cache line. The highly transient nature of the data stored in L1 data cache aides this process of recovery upon using iRMW. A unique feature of iRMW is its intelligent use of low-leakage & NBTI-tolerant embedded-DRAM cells as an alternative to SRAM-cells for storing important state information. Our experiments conducted using SPEC2006 and PhysicsBench workloads show that on-average the cache failure probability can be reduced by 22%, 33% and 36% after two, four and eight years of processor usage respectively. In addition to being extremely power-frugal, use of eDRAM reduces total area footprint of iRMW tremendously.

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“…Namely, it allows for the use of innovative software approaches as a means of alleviating the NBTI-induced aging effects. In contrast to previous works that focus on pure circuit/architectural solutions (e.g., [7,22]), in this article we investigate new software controlled NBTI-aware data managing solutions for low-power SPMs. While hardware-based solutions such as those proposed in [22] and [7] do show substantial improvements in aging, a software scheme has clear advantage over these other solutions in that it does not impact cache timing (which is often on the critical path) and can be implemented on top of existing memory structures.…”

mentioning

confidence: 94%

“…Following the need for reliable and low-power memory architectures, very recent works [6,22] have shown how conventional power-management schemes for leakage reduction [16,21] can also offer a valuable solution to mitigate NBTI-induced aging effects on memories. Dynamic Voltage Scaling (DVS) has been demonstrated to be a particularly efficient approach; it provides a good trade-off between leakage savings and aging, while minimizing the design overheads.…”

mentioning

confidence: 99%

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems

et al. 2012

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The push to embed reliable and low-power memories architectures into modern systems-on-chip is driving the EDA community to develop new design techniques and circuit solutions that can concurrently optimize aging effects due to Negative Bias Temperature Instability (NBTI), and static power consumption due to leakage mechanisms. While recent works have shown how conventional leakage optimization techniques can help mitigate NBTI-induced aging effects on cache memories, in this paper we focus specifically on scratchpad memory (SPM) and present novel software approaches as a means of alleviating the NBTI-induced aging effects. In particular, we demonstrate how intelligent software directed data allocation strategies can extend the lifetime of partitioned SPMs by means of distributing the idleness across the memory sub-banks.

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Investigating the impact of NBTI on different power saving cache strategies

Cited by 35 publications

References 17 publications

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems

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