Interface tasks oriented 8-bit soft-core processor

Gomez-Cornejo, Julen; Zuloaga, Aitzol; Bidarte, Unai; Jiménez, Jaime; Kretzschmar, Uli

doi:10.1145/2451636.2451640

Cited by 4 publications

(3 citation statements)

References 7 publications

(7 reference statements)

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“…Next, the Location Constraints Flow has been validated. In this case, a TMR design with three instances of a PICDiY soft-core processor [27] has been implemented in three reconfigurable regions (Pblock0, Pblock1 and Pblock2). In this first implementation, all resources of each instance have been freely placed by the tool.…”

Section: Experimental Setup and Physical Validationmentioning

confidence: 99%

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

et al. 2022

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This paper proposes a methodology to access data and manage the content of distributed memories in FPGA designs through the configuration bitstream. Thanks to the methods proposed, it is possible to read and write the data content of registers without using the in/out ports of registers in a straightforward fashion. Hence, it offers the possibility of performing several operations, such as, to load, copy or compare the information stored in registers without the necessity of physical interconnections. This work includes two flows that simplify the designing process when using the proposed approach: while the first enables the protection or unprotection of writing on different partial regions through the bitstream, the second permits homogeneous instances of a design implemented in different reconfigurable regions to be obtained without losing efficiency. The approach is based and has been physically validated on the ZYNQ from Xilinx, and when using partially reconfigurable designs, it does not affect the hardware overhead nor the maximum operating frequency of the design.

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Section: Experimental Setup and Physical Validationmentioning

confidence: 99%

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

et al. 2022

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“…Some processors like the Picoblaze [24] are platform dependent and do not represent a valid solution for different FPGA vendors. Thus, it has been decided to use the processor proposed in [25] as a basis for the proposed lockstep architecture. This processor offers a platform independence and low resources usage with a simply architecture, which is very attractive to be adapted to the needs of the approach.…”

Section: Design and Implementation Of The Fault-tolerant Architecmentioning

confidence: 99%

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

Gomez-Cornejo

Zuloaga

Kretzschmar

et al. 2013

IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society

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This paper presents a new approach of the lockstep technique to protect FPGA designs with soft core processors against Single Event Upsets (SEUs) and Single-Event Transients (SETs). One of the biggest drawbacks when using the lockstep technique is the processor context saving and restoring latency. Our approach minimizes the latency thanks to a specific architecture and a specifically adapted 8-bit soft core processor. The proposed architecture is also hardened by using ECC code in memory elements. In this way, this approach combines the benefits of fast SEUs detection with fast restoration of the device functionality. This is demonstrated by running a serial communication application hardened with the new lockstep approach and comparing the results with a Triple Modular Redundancy (TMR) implementation. The design has been implemented in a Xilinx Virtex-5 FPGA.

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“…• Xilinx PicoBlaze [188] • Lattice Mico8 [189] • Navre [190] and pAVR [191]: Atmel AVR compatible 8-bit RISC hosted on OpenCores.org • MCL86, MCL51, and MCL65 [192]: Intel 8088/8086, 8051, and MOS 6502 compatible There are also academic-level cores which we mention a few: "8-bit interface task oriented processor [193], an 8-bit RISC core [167], and an 8-bit MiniMIPS [194] for educational purposes , a soft-core with dual accumulator [195]". Among all cores mentioned, only Xilinx and Lattice are industry-level 8-bit cores, and consequently most probable to be bug-free.…”

Section: Resultsmentioning

confidence: 99%

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Ali¹

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The reconfigurable computing (RC) aims to combine the flexibility of General-Purpose Processor (GPP) with performance of Application Specific Integrated Circuits (ASIC). There are several architectures proposed since RC’s inception in 1960s, but all have failed to become mainstream. The main factor preventing RC to become common practice is its requirement for implementers of algorithms (programmers) to be familiar with hardware design. In RC, a hardened processor cooperates with a dynamic reconfigurable Hardware Accelerator (HA) which is implemented on Field-Programmable Gate Array (FPGA). The HA implements crucial software kernel on hardware to increase performance and its design demands digital circuit expertise. In this paper a novel RC architecture is proposed that keeps the decades old programming practices intact while harnessing the power of HA. The architecture uses LLVM compiler infrastructure to receive an algorithm and then outputs the equivalent machine language, it then finds the most frequent instruction pairs and generates equivalent RC circuit called “Miniature Accelerator (MA)”. The instruction pairs are dynamically removed from pipeline and MA computed result replaces them in parallel. To demonstrate the concept the Fast Fourier Transform (FFT) algorithm which is core Digital signal processing (DSP) kernel is written in C and then executed on an ARM Cortex-M0. The execution of FFT function is improved by 14.12%. The proposed adaptive processor is fully backward compatible, compilation is automated, and no modification of exiting software or established programming paradigms is required.

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Interface tasks oriented 8-bit soft-core processor

Cited by 4 publications

References 7 publications

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

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