Interface state energy distribution and Pb defects at Si(110)/SiO2 interfaces: Comparison to (111) and (100) silicon orientations

Abstract

Traps at the (110)Si/SiO2 interface are investigated by combining electrical methods with electron spin resonance (ESR) measurements, and the results are compared to the well studied (100) and (111)Si/SiO2 interfaces. At all three Si crystal faces, the interface trap density Dit as function of energy E in the Si band gap exhibits two peaks at about 0.25 and 0.85 eV above the Si valence band, found to be well correlated with Pb(0) centers (Si3≡Si• defects). By comparing capacitance-voltage (CV) curves at 300 and 77 K of both n- and p-type samples, the Pb(0) defects are confirmed to be amphoteric. Effective passivation of interface traps by H2 annealing suggests that Pb0 defects are responsible for most of interface traps observed in (110)Si/SiO2. The truly amphoteric behavior, implying that one Pb0 defect delivers two interface trap levels, was observed for the (100) and (111)Si faces but not for the (110) face. The estimated interface trap density Nit at the (110)Si/SiO2 interface oxidized at 930 °C is (6.7±0.5)×1012, while the Pb0 density as determined by ESR is about (6±1)×1012 cm−2. Lowering of the oxidation temperature leads to further reduction in the electrically active Pb0 centers fraction at the (110)Si/SiO2 interface.

Observation of peripheral charge induced low frequency capacitance-voltage behaviour in metal-oxide-semiconductor capacitors on Si and GaAs substrates

“…The peak energy positions are consistent with those expected for P b dangling bond defects, as reported extensively in the literature. 14,[20][21][22][23][24][25][26][27] It is important to state that the peripheral inversion effect is not unique to the MgO/Si system or the FUSI processing used for the MgO sample set. To illustrate this, results are now presented showing evidence of peripheral inversion effects for a different oxide/Si MOS system, and where very different processing steps were used in the device fabrication, as described earlier in the experimental section.…”

Anomalous scaling of spin accumulation in ferromagnetic tunnel devices with silicon and germanium

“…To obtain a scaling of the spin signal (due to back flow) up to tunnel resistances of 10 [41], but this requires a final anneal in hydrogen forming gas, which we do not apply. In fact, for the Si/Al 2 O 3 interfaces in our devices, an interface state density of about 10 13 states/eV cm 2 was previously determined [8], requiring τ ls s to be even larger (100 μs).…”

Inherent interface defects in thermal (211)Si/SiO2:29Si hyperfine interaction

“…ESR, as a unique tool, has allowed identification of Si dangling bond (DB) interface defects, denoted as P b -type centers in ESR jargon (generic entity Si 3 ≡Si•, where the dot represents an unpaired electron located in an unpaired sp 3 -like hybrid). They represent the dominant system of intrinsic (mismatch induced) interface defects [7,8] operating as electrically detrimental traps [9][10][11][12][13][14]. The current work deals with the thermal (211)Si/SiO 2 structure, where, as expected, P b -type defects are observed.…”

“…It thus appears that oxidation at a temperature T ox 750 C is required to minimize the P b0 (211) density, that is, realize the standard thermal (211)Si/SiO 2 interface defect level. In regard of device application, given the wellknown devastating electrical influence on charge carriers of P b -type interface defects [9][10][11][12][13][14], this would represent the optimal thermally grown (211)Si/SiO 2 interface troubled by the lowest number of inherent P b -type defects attainable through optimized thermal oxidation. .0077 for T ox~4 00°C.…”