Interface specification with temporal logic

Abstract

This paper describes developmentsand experience in the ESPRIT project 1283: "VDM for Interfaces of the PCTE". It shows the way temporal logic is used in combination with the relational VDM method in order to write interface specifications for large reactive systems. It is shown tlhat in this way a specification can be written both usable for implementors and users of an interface. The ability to dlistinguish within the logic between an internal and an external action appears to be very important.