Integration of a cellular handset power amplifier and a DC/DC converter in a Silicon-On-Insulator (SOI) technology

Tombak, A.; Baeten, R.J.; Jorgenson, J.; Dening, D. C.

doi:10.1109/rfic.2008.4561466

Cited by 20 publications

(5 citation statements)

References 6 publications

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“…The bias controller circuit is usually implemented on a CMOS platform. The penalty paid is in complexity as dual process is needed for the PA realization [40,41]. There has been a continuous attempt to use an all CMOS process to reduce the design cost [42].…”

Section: Average Bias Tracking (Abt)mentioning

confidence: 99%

Energy saving power amplifier design methodologies for mobile wireless communications

Eswaran

Ramiah

Kanesan

et al. 2015

Renewable and Sustainable Energy Reviews

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Section: Average Bias Tracking (Abt)mentioning

confidence: 99%

Energy saving power amplifier design methodologies for mobile wireless communications

Eswaran

Ramiah

Kanesan

et al. 2015

Renewable and Sustainable Energy Reviews

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“…This situation is especially critical for stand-alone switching modulator controlled by the conventional pulse-width modulation (PWM) scheme with a constant switching frequency. To mitigate the impact of the spurious noise of the stand-alone DC-DC converters, several techniques of altering the switching behaviors of DC-DC converters have been reported, such as the frequency hopping/stepping/ dithering in [33]- [36]. In our linear-assisted switching modulator, however, the switching ripples can be suppressed by the linear stage.…”

Section: B Switching Stage Designmentioning

confidence: 99%

“…The emission noise can be further suppressed by adding extra filtering or duplexer isolation. We also expect that, by using the silicon-on-insulator (SOI) technology or technology with high-resistivity silicon substrate, the noise coupled from the buck converter to the PA can be effectively reduced [33]. We would like to point out again that the switching ripples of the envelope modulator would be more critical in EER-PA systems, requiring the linear stage of much wider bandwidth (e.g., in the work of [4]), or even a plain linear regulator (e.g., in the work of [3]) in the system, which will inevitably lower the overall system efficiency.…”

Section: A Efficiency and Linearity For Lte Signalsmentioning

confidence: 99%

Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

Lopez

Schecht

et al. 2012

IEEE J. Solid-State Circuits

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This paper presents the design insights for the implementation of a fully monolithic radio frequency (RF) power amplifier (PA) using both envelope-tracking (ET) and transistor resizing techniques for long-term evolution (LTE) applications. At the low output power region, some of the power cells in the PA can be disabled to further save power consumption, thus enhancing the efficiency from a traditional ET-PA. Our ET-PA system is first realized with a two-chip solution, consisting of a high voltage envelope modulator fabricated in a 0.35 m Bipolar-CMOS-DMOS (BCD) technology, and a differential cascode PA in a 0.35 m SiGe BiCMOS technology. This two-chip solution of the ET-PA is to showcase the effective efficiency enhancement of using the transistor resizing method. In the second design, a CMOS envelope modulator is integrated with the cascode PA on the same die in the 0.35 m SiGe BiCMOS technology. Some insights are demonstrated regarding the optimization of the envelope modulator specific to our cascode PA for LTE broadband signals, where the finite bandwidth and the switching frequency of the envelope modulator are considered for achieving the minimal error-vector magnitude (EVM) and spurious noise. The fully monolithic BiCMOS ET-PA reaches the maximum linear output power ( ) of 24 dBm and 23.4 dBm with overall power-added-efficiency (PAE) of 41% and 38% for the LTE 16QAM 5 MHz and 10 MHz signals at 1.9 GHz, respectively, without needing predistortion. At the low power mode of our ET-PA, an additional PAE enhancement of 4% is obtained at of 16-20 dBm by disabling some of the PA power cells. Our fully monolithic ET-PA satisfies the LTE 16QAM linearity specs with high efficiency. Index Terms-Bipolar-CMOS-DMOS (BCD), cascode power amplifier (PA), envelope modulator, envelope-tracking (ET), long-term evolution (LTE), low power mode, SiGe BiCMOS, transistor resizing.

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“…In recent years SOI switches have received widespread acceptance in the cellular handset market [3], [4], [5]. Antenna switches in bulk CMOS have been researched, but suffer from lower power handling and increased insertion loss.…”

Section: A Antenna Switch Integration In Hr Soi Cmosmentioning

confidence: 99%

“…Since high performance antenna switches have already been integrated on SOI [2] and the feasibility of SOI power amplifiers has also been reported very recently [3], we will focus our work on the implementation of harmonic filters on SOI, and then propose a benchmark with IPDs technologies II. HR SOI CMOS TECHNOLOGY DESCRIPTION FEMs require a combination of good isolation, high power/high voltage handling, high efficiency, good passive elements and complementary devices for digital integration.…”

Section: Introductionmentioning

confidence: 99%

Small-size low losses GSM and DCS harmonic filters integrated in a low cost 130 nm high resistivity SOI CMOS technology

Gianesello

Durand

Bon

et al. 2010

2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

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RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon [1]. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus our investigation on high performance passives functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, GSM and DCS harmonic filters have been achieved in a 130 nm SOI CMOS technology. Measured performances (insertion losses ~1dB and harmonic rejection greater than 30 dB) are clearly competitive with most commercially available Integrated Device Passive (IPD) solutions.Index Terms -SOI, harmonic filter, front end module, high resistivity, integrated passive.

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Integration of a cellular handset power amplifier and a DC/DC converter in a Silicon-On-Insulator (SOI) technology

Cited by 20 publications

References 6 publications

Energy saving power amplifier design methodologies for mobile wireless communications

Energy saving power amplifier design methodologies for mobile wireless communications

Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

Small-size low losses GSM and DCS harmonic filters integrated in a low cost 130 nm high resistivity SOI CMOS technology

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