Insights into the operation of negative capacitance FinFET for low power logic applications

Jaisawal, Rajeewa Kumar; Kondekar, P. N.; Yadav, Sameer; Upadhyay, Pranshoo; Awadhiya, Bhaskar; Rathore, Sunil

doi:10.1016/j.mejo.2021.105321

Cited by 25 publications

(14 citation statements)

References 21 publications

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“…It can be seen that at T FE =8 nm,h y s t e r e s i s appears to occur in the output characteristics. This is due to a mismatch in the ferroelectric capacitance and internal total baseline FinFET capacitances (discussed in 2.1), which should be avoided if such an NCFinFET device is to be used for logic and memory applications [46]. The unique feature: negative DIBL [47] and NDR [48]i nt h e NCFinFET indicating the small model's capacity is shown in Fig.…”

Section: Compact Modeling Methodology Of Ncfetmentioning

confidence: 99%

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Yadav

Kondekar

Awadhiya

et al. 2022

Preprint

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In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14nm conventional FinFET to form NC-FinFET. Static and dynamic behaviour of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET-based SRAM, 6T-NCSRAM exhibits distinct behaviour during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

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Section: Compact Modeling Methodology Of Ncfetmentioning

confidence: 99%

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Yadav

Kondekar

Awadhiya

et al. 2022

Preprint

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“…As studied, ferroelectric Junction less FET (Fe-JLFET) is another promising semiconductor device where a layer of ferroelectric material is incorporated in the middle of the gate stack, which helps in amplification of gate voltage instead of a drop in voltage in the transistors [8,9]. This rise in internal voltage helps the subthreshold swing value to go beyond its fundamental limit, which in turn increases the overall gate negative capacitance, thereby increasing the switching power consumption of the device as compared with the traditional CMOS transistors.…”

Section: Introductionmentioning

confidence: 99%

RF with linearity and non-linearity parameter analysis of gate all around negative capacitance junction less FET (GAA-NC-JLFET) for different ferroelectric thickness

2022

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A novel Gate All Around Negative Capacitance Junction less FET (GAA-NC-JLFET) is proposed in this work, where different RF/Analog, Linear, and Non-linear parameters were investigated for different ferroelectric thickness in depth. The simulation result is calibrated with the available experimental data from literature. Adding a layer of ferroelectric material to a JLFET is a good means of decreasing short channel effects when compared to typical GAA JLFETs. The effect of ferroelectric layer thickness on DC parameters such as drain current (IDS), subthreshold swing (SS), threshold voltage (Vth), and Ion/Ioff as well as linear parameters such as transconductance coefficients (gm2 and gm3), voltage intercept points (VIP2 and VIP3), and input intercept point (IIP3) have been studied. Furthermore, this paper investigates non-linearity parameters such as harmonic distortion and intermodulation distortion in relation to various ferroelectric thicknesses. The TCAD device simulator was extensively used to conduct this analysis, and the results revealed that increasing the ferroelectric layer resulted in a significant improvement in the values of RF and linear parameters, as well as a decrease in the values of non-linearity parameter values, resulting in an increase in the device's linearity, which can be used in wide range of RFIC applications.

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“…devices such as smartphones, and neuromorphic computing [1][2][3]. The downscaled FETs geometry is continuously evolving from planar MOSFET to nonplanar FinFET [4][5][6], to gate-all-around (GAA) nanowire, and stacked nanosheet FET (NS-FET) [7] for better and improved gate controllability of the structure. The thermal management of the shrinking FETs is an arduous concern due to the self-heating effect (SHE) observed in gate surrounded structures like FinFET, nanowire [8], and NS-FET [9], which will increase device temperature [10].…”

Section: Introductionmentioning

confidence: 99%

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

Rathore¹,

Jaisawal²,

Suryavanshi³

et al. 2022

Semicond. Sci. Technol.

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Self-heating effect (SHE) is a severe issue in advanced nano-scaled devices such as stacked nanosheet field-effect transistors (NS-FET), which raises the device temperature (TD), that ultimately affects the key electrical characteristics, i.e., threshold voltage (VT), DIBL, subthreshold slope (SS), IOFF, ION, etc. SHE puts design constraints in the advanced CMOS logic devices and circuits. In this paper, we thoroughly investigated the impact of ambient temperature and interface thermal contact resistance induced-self heating effect in the NS-FET using extensive numerical simulations. The weak electron-phonon coupling, phonon scattering, and the ambient temperature-induced joule energy directly coupled with thermal contact resistance cause the SHE-induced thermal degradation, which increases the device temperature (TD) and affects the device reliability. The baseline NS-FET is well-calibrated with the experimental data and 3D quantum corrected drift-diffusion coupled hydrodynamic and thermodynamic transport models is used in our TCAD framework to estimate the impact of ambient temperature and interface thermal contact resistance on the device performance. Moreover, we also evaluate the SHE-induced performance comparison of NS-FET with conventional FinFET and found that thermal degradation in NS-FET potentially worsen the electrical characteristics. Thus, a detailed TCAD analysis shows that the ambient temperature and interface thermal contact resistances deteriorate the effective thermal resistance (Reff) and device performance metrics.

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Insights into the operation of negative capacitance FinFET for low power logic applications

Cited by 25 publications

References 21 publications

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

RF with linearity and non-linearity parameter analysis of gate all around negative capacitance junction less FET (GAA-NC-JLFET) for different ferroelectric thickness

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

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