Input waveform slope effects in CMOS delays

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

“…Actually, characterizing the DDM completely also implies the characterization of the normal propagation delay (t p0 ), and the value of t p0 depends on both C L and τ in [1,4]. Our main objective is to analyse the behaviour of t p0 in order to implement it, as part of DDM, in a logic timing simulator (HALOTIS) focused on the simulation of circuits based on standard cell libraries.…”

“…In the field of logic simulation of digital CMOS circuits, delay models exist that take into account most issues affecting accuracy [1][2][3][4]: low voltage, submicron and deep submicron devices, transition waveform, etc. There are also dynamic effects, the most important being the so-called input collisions [5], which happens when two or more input signals change almost simultaneously.…”

Delay modelling improvement for low voltage applications

“…These models did not include the influence of short circuit currents and were limited to fast input ramps. Further improvement has been obtained in [4], where simple technology dependent corrections extend the application range of the preceding models over a large domain of configurations. Recently Jeppson [5], in an attempt to consider exact wave form and coupling capacitances obtained a physical expression equivalent to a second order development of the rationale function of [4].…”

“…This is clearly shown in figure 1 which illustrates the simulated variations of the propagation delay of an inverter (with constant load), controlled by different input ramps. The fraction of input delay to be considered, has been tentatively physically defined in [4], as the time spent by the input ramp to create sufficient current unbalance in the controlled device, to equilibrate the output load (thus allowing output voltage variation). In fact, for usual tapering factors, it has been observed that this unbalance is sufficient only when the P (or N) is completely switched off.…”

HALOTIS: High Accuracy Logic TIming simulator with inertial and degradation delay model

“…Currently, there exist accurate delay models for CMOS digital circuits which take account of most modern issues [1,2,3,4]: low voltage operation, sub-micron and deep sub-micron devices, transition waveforms, etc. Besides these effects, there are also dynamic situations which should be handled by the delay model.…”