Influence of non-inert electrode thickness on the performance of complementary resistive switching in AlOxNy-based RRAM

Abstract

This Letter investigates the effect of non-inert electrode thickness on the performance of complementary resistive switching (CRS). Five devices with different Ta electrode thicknesses (0, 2, 5, 10, and 20-nm) are fabricated. For devices with 2, 5, and 10-nm electrode thicknesses, CRS behavior can be obtained through an evolution process, while devices with 0 and 20-nm Ta electrode thicknesses always maintain stable bipolar resistive switching behavior. By analyzing the evolution process and current conduction mechanisms, the influence of non-inert electrode thickness on the performance of CRS is studied, and different oxidation degrees of a non-inert electrode are used to explain the different resistive switching performance in these devices. Aside from that, the model is verified by applying an asymmetric voltage sweeping method. This paper further clarifies the physical mechanism of CRS behavior in non-inert electrode resistive random access memory and provides a way to optimize the performance of CRS behavior.

Understanding the complementary resistive switching in egg albumen-based single sandwich structure with non-inert Al electrode

“…Device structure simplification was achieved in oxide-based tri-layer geometries, such as TiO x /TiON/TiO x [8], ZnO/SiO x /ZnO [9], and TiO x /TiO 2 /TiO x [10], and double-layer geometries, such as Ta 2 O 5−x /TaO y [11] and TiO 2−x /TiN x O y [12]. Furthermore, CRS behaviors have also been demonstrated in single sandwich structures using inert electrodes [13][14][15][16][17][18] and non-inert electrodes [19,20]. Notably, CRS characteristics are mainly realized in oxide-based heterostructures, which may suffer from the disadvantages of brittleness, incompatibility, and high-cost fabrication [21].…”

Multibit, Lead‐Free Cs2SnI6 Resistive Random Access Memory with Self‐Compliance for Improved Accuracy in Binary Neural Network Application

“…These include the thickness of the material, [15] non-stoichiometric chemical composition, notably oxygen concentration, [16] defect concentration (like oxygen vacancies), [14,15] intrinsic defects, the strategic control over 1D or spatially restricted conducting filament growth seen in materials like CuO and ZnO nanowires, [14,17] physical parameters such as the dielectric constant [15] and thermal conductivity, [33] the presence of a metallic phase or the doping with metal ions, [17] and various process parameters. [14] Such process parameters include annealing temperature and atmosphere, [16] the material and thickness of the top electrode, [34,35] the area of the top electrode pad, [36] bilayer device configuration, and controlled joule heating. Additionally, the formation of an interfacial layer at the interface of the top electrode and RS layer has also been understood to be a significant factor.…”

SiNx‐Based Digital–Analog Hybrid Resistive Random Access Memory via Heterogeneous Integration

“…[25,26] In our previous experiments, the Pt/SiN x /Ta/Ru structure is a digital RRAM and the TiN/SiN x/ Ta/Ru structure is an analog RRAM. [27] In this work, digital RRAM and analog RRAM are integrated into a single RRAM using heterogeneous integration. DOI: 10.1002/pssa.202300964 Herein, a digital-analog hybrid resistive random-access memory (RRAM) is prepared by integrating the structurally similar SiN x -based digital-type RRAM with analog-type RRAM by heterogeneous integration method.…”

“…In our previous experiments, the Pt/SiN x /Ta/Ru structure is a digital RRAM and the TiN/SiN x / Ta/Ru structure is an analog RRAM. [ 27 ] In this work, digital RRAM and analog RRAM are integrated into a single RRAM using heterogeneous integration. The I–V characteristics were analyzed and the conductive mechanism was fitted.…”