Indium penetration through thermally grown silicon oxide

Chang, Ruey-Dar; Wang, Hsin-Jen

doi:10.1016/j.vacuum.2015.01.010

Cited by 3 publications

(3 citation statements)

References 11 publications

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“…In contrast, by capping the SiO 2 with an Si 3 N 4 layer, indium diffusion is effectively reduced. (54)(55) We have used a Qtac 100 (Ion-TOF), in which a low dose (10 13 to 10 14 ions/cm 2 ) of ions with moderate energies (3-keV 4 He + and 5-keV Ne + ) is focused on the surface. Backscattered ions are then energy analyzed by time-of-flight detection.…”

Section: Diffusion Of Iii-v Elements Through High-kmentioning

confidence: 99%

“…It is postulated that the hydrogen from the precursor used in the CVD silicon dioxide deposition may enhance the diffusion process. In contrast, by capping the SiO 2 with an Si 3 N 4 layer, indium diffusion is effectively reduced (54)(55). We have used a Qtac 100 (Ion-TOF), in which a low dose (10 13 to 10 14 ions/cm 2 ) of ions with moderate energies (3-keV4 He + and 5-keV Ne + ) is focused on the surface.…”

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confidence: 99%

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Chemical Nature and Control of High-k Dielectric/III-V Interfaces

Cabrera

Chabal

2015

ECS Trans.

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A number of surface treatments and deposition techniques have been developed to control the interface of high-k/III-V semiconductor gate stacks, which is critical to III-V-based device performance. While electrical measurements have demonstrated the value of these specific processes, there has been little work on the chemical composition of III-V surfaces and interfaces. Using primarily infrared absorption spectroscopy, we have focused on two aspects associated with oxide growth processing: 1) chemical passivation of the interface with monolayer engineering, and 2) barrier for III-V elemental diffusion. We find for example that incorporation of silicon layer by gas phase processing prior to atomic layer deposition of Al 2 O 3 on an oxidized InP surface is effective in reducing an interface layer, composed of dative P=O•••Al and covalent P-O-Al bonds. However, such barriers are not as effective in preventing indium diffusion through high-k dielectrics either during ALD growth or upon post-annealing.

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Section: Diffusion Of Iii-v Elements Through High-kmentioning

confidence: 99%

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confidence: 99%

Chemical Nature and Control of High-k Dielectric/III-V Interfaces

Cabrera

Chabal

2015

ECS Trans.

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“…6) However, indium atoms would diffuse randomly under high-temperature annealing (>800 °C). 1,7) Current-stress or thermal-current-costress tests have been utilized as a tool for investigating the microstructure of InGaN devices. [8][9][10][11][12][13][14] Interestingly, on the basis of the results of the short-term dc-stress ageing of blue LEDs, Meneghini's group proposed a hypothesis that the current injected into the active region with a density of 32 A=cm 2 was capable of modifying defects at room temperature (RT), leading to the decrease in EQE at low currents.…”

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Evolution of crystal imperfections during current-stress ageing tests of green InGaN light-emitting diodes

Lin

Peng

Zhu

et al. 2016

Appl. Phys. Express

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We perform ageing tests under high current on several green InGaN light-emitting diodes and compare the luminous homogeneities of chip surfaces, shapes of external quantum efficiency (EQE) curves, and electroluminescence spectra during different ageing stages. By curve fittings to the EQE curves, with the ABC and two-level models, we discover that a high injection current density can modify the defect configuration in quantum wells even at room temperature, as high-temperature annealing can. For In-rich devices, the removal of localization centers is another origin of luminous intensity decay in addition to the formation of point defects.

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