In-chip overlay metrology

Ku, Yi-Sha; Tung, Chiou-Kou; Li, Y. P.; Pang, Hanbin; Smith, Nigel; Binns, Lewis A.; Rigden, Timothy C.; Reynolds, Greg; Fink, Hans‐Werner

doi:10.1117/12.655953

Cited by 5 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, there is a relationship between the asymmetry of the image and overlay error so that overlay error can actually be determined or calculated based on asymmetry [4][5][6]. The symmetry of the image, F, is the smallest value of the root-mean-square difference of intensities at equal distances about any point s within the image(equation 1).…”

Section: A the Measurement Algorithmmentioning

confidence: 99%

Overlay metrology for next generation lithography at CMS

Ku¹,

Tai²,

Chang³

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

View full text Add to dashboard Cite

The Center for Measurement Standards (CMS) has a research program in optical overlay metrology. The main goal of this work is to improve overlay measurement accuracy. Two main threads are developed to the work -novel in-chip overlay target design, and best algorithm. The former is hoped to prove a capability for measuring overlay error inside the active area of product devices. The later is for extracting the most from image detail.

show abstract

Section: A the Measurement Algorithmmentioning

confidence: 99%

Overlay metrology for next generation lithography at CMS

Ku¹,

Tai²,

Chang³

2007

2007 7th IEEE Conference on Nanotechnology (IEEE NANO)

View full text Add to dashboard Cite

show abstract

“…However, there is a relationship between the asymmetry of the image and overlay error so that overlay error can actually be determined or calculated based on asymmetry 4,5,6 . The symmetry of the image, F, is the smallest value of the root-mean-square difference of intensities at equal distances about any point s within the image (equation 1).…”

Section: The Measurement Algorithmmentioning

confidence: 99%

“…In earlier papers 4,5,7 we demonstrated the feasibility of measuring overlay using the effect of proximity in small targets on image symmetry. These targets are much smaller (3µm or less) than the traditional targets and so increase the feasibility to measure overlay within the device area of product wafers.…”

Section: Introductionmentioning

confidence: 98%

In-chip overlay metrology for 45nm processes

Pang

Smith³

et al. 2007

SPIE Proceedings

Self Cite

View full text Add to dashboard Cite

The feasibility of measuring overlay using small (between 1x1µm and 3x3µm total size) targets has been demonstrated 4 . The symmetry of the image of isolated test features changes with overlay offset. The targets are small enough to be positioned within active areas of the device, and total measurement uncertainty (TMU) is sufficient to allow these targets to be used in characterizing overlay variations in the active device. In this paper we describe further development of this technique and its application to overlay control in 45nm processes. A simple image model has been used to predict how the target images change with overlay error, and to study the unwanted effects of process variation on the measurement. In order to ensure the accuracy of measurements made using the in-chip targets it is necessary to provide for dynamic calibration of the symmetry-to-overlay response. This calibration can be readily achieved by printing multiple targets close together, with each target having a programmed offset that differs by a small amount. In our tests we have used triplets of targets with programmed offsets of 30nm, 50nm and 70nm. Normal targets are printed with a programmed offset of 50nm.A test reticle was designed for double-pass printing of a range of in-chip targets with different sizes and component dimensions, and with designed overlay offsets of 0nm to 100nm in 4nm steps. Standard bar-in-bar targets were printed with every in-chip target to allow the change of symmetry with overlay to be measured directly. Wafers were printed using a 45nm process poly-to-STI stack. Measurements were made in multiple fields and from multiple wafers using an unmodified Nanometrics Caliper élan overlay tool. The test wafers were printed with extremes of process variation. Correlation of the measured image symmetry to the programmed offset under different process conditions shows that the response is sensitive to film changes, as predicted by the image model.Results from production wafers show that the effect of normal process variation is small enough that calibration is not necessary at every location. Placing a few calibration targets in the scribe lines of the device is more than sufficient, allowing the smallest possible space requirement for measurement inside the active area of the device.Detailed study of the change in overlay with programmed offset along a line of test samples with the same design properties shows short-scale variations of order 1-5nm. According to the 2005 ITRS 1 these variations account for nearly 50% of the overlay budget for a 45nm process. This effect cannot be described by any model where overlay variations are purely a mathematical function of position, and in process control at this node it will become necessary to use characterization of overlay by measurement instead of models.

show abstract

In-die overlay metrology method using defect review SEM images

Kwon

Mun

et al. 2013

SPIE Proceedings

View full text Add to dashboard Cite

In-chip overlay metrology

Cited by 5 publications

References 0 publications

Overlay metrology for next generation lithography at CMS

Overlay metrology for next generation lithography at CMS

In-chip overlay metrology for 45nm processes

In-die overlay metrology method using defect review SEM images

Contact Info

Product

Resources

About