Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

Muthana, P.; Srinivasan, Krishna; Engin, A. Ege; Swaminathan, Madhavan; Tummala, Rao; Sundaram, Venkatesh; Wiedenman, B.; Amey, Daniel I.; Dietz, K.H.; Banerji, Sounak

doi:10.1109/tadvp.2008.920651

Cited by 24 publications

(10 citation statements)

References 16 publications

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“…Higher dielectric constant materials have also become available for lower impedance applications. Acting as parallel plate capacitors, the thinner layers and increased dielectric constant provide a significant increase in capacitance, and the planes used in power distribution networks reduce inductance and resistance [5]. An effective, embedded passive solution that directly embeds discrete surface-mount capacitors into the package substrate is presented Fig.…”

Section: Embedded Decoupling Capacitormentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.

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Section: Embedded Decoupling Capacitormentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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“…To mitigate PPW modes, various techniques such as decoupling capacitors, slotted planes, and electromagnetic bandgap (EBG) structures have been presented [1][2][3][4][5][6][7][8][9]. Among these, EBG structures are prominent approaches for suppressing PPW modes over wideband frequency ranges.…”

Section: Introductionmentioning

confidence: 99%

A Miniaturized Electromagnetic Bandgap Structure Using an Inductance-Enhanced Patch for Suppression of Parallel Plate Modes in Packages and PCBs

Kim

2018

Electronics

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Abstract:In the packages and printed circuit boards (PCBs) of high-speed and mixed-signal electronics, parallel plate waveguides (PPWs) are frequently used as the power/ground plane pair, resulting in a significant problem of electrical switching noise such as simultaneous switching noise and ground bounce noise. This noise inevitably deteriorates system performance. In this paper, we propose an electromagnetic bandgap (EBG) structure using an inductance-enhanced patch (IEP) to suppress PPW modes in high-speed and compact packages and PCBs. The noise suppression characteristics of the proposed IEP-EBG structure were thoroughly analyzed using a dispersion diagram based on a full-wave simulation as well as an equivalent circuit model of a unit cell structure with a Floquet boundary condition. The proposed IEP-EBG structure has the advantages of substantial reductions in the low cut-off frequency of the first stopband as well as unit cell size when compared to a conventional mushroom-type EBG structure without the inductance-enhanced technique. The suppression of the PPW modes of the proposed IEP-EBG structure was verified using measurements of scattering parameters. In the measurements, the low and high cut-off frequencies of the first stopband of the IEP-EBG structure were found to be 1.55 GHz and 2.48 GHz, respectively, while those of the conventional mushroom type EBG structure were 3.52 GHz and 5.3 GHz. For the low cut-off frequency, a 56% reduction was achieved, resulting in substantial miniaturization suitable for compact packages and PCBs.

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“…Specifically for System-in-Package (SiP), embedded capacitors are becoming one of the most critical technologies to achieve effective system integration [1][2][3]. In addition to application in SiP, embedded capacitors are also widely used for filtering and decoupling of high frequency integrated circuits primarily because of their greatly reduced parasitics compared with surface mounted capacitors [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

The development of wafer-level 3D high-density junction capacitor for passive device integration in SiP

Wang

et al. 2012

2012 4th Electronic System-Integration Technology Conference

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Rapidly growing performance and mixed-signal integration is driving the requirement for product and component miniaturization in electronics applications. Embedded passive technology is a potentially attractive solution to replace discrete passives, due to low parasitic parameters, homogeneous integration and small form factor. Embedded capacitors are widely used in a broad range of applications including filtering, tuning and powerbus decoupling in the substrate. In this paper, MicroElectron-Mechanical System (MEMS) process based on silicon 3D patterns etching and thermal diffusion doping of silicon is used to fabricate a high-density silicon-embedded capacitor. Deep 3D trench structures formed by the Bosch process in inductively coupled plasma (ICP) increase the effective capacitance area, thus enhancing the capacitance areal density. This paper reports on the fabrication process and electrical properties of silicon trench capacitors and achievable capacitance densities. Measurement results indicate that the 3D-structured capacitor can attain a capacitance density of 12nF/mm 2 , which is 10-12 times larger than that of planar semiconductor capacitors. This type of capacitor is a good candidate for high-power decoupling, filtering, and electrostatic discharge (ESD) protection, and may be preferred over SMT capacitors in electronics applications with form factor requirements.

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Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

Cited by 24 publications

References 16 publications

TSV Decoupling Schemes

TSV Decoupling Schemes

A Miniaturized Electromagnetic Bandgap Structure Using an Inductance-Enhanced Patch for Suppression of Parallel Plate Modes in Packages and PCBs

The development of wafer-level 3D high-density junction capacitor for passive device integration in SiP

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