Improvement of dual rail logic as a countermeasure against DPA

Razafindraibe, Alin; Robert, Michel; Maurine, Philippe

doi:10.1109/vlsisoc.2007.4402510

Cited by 21 publications

(37 citation statements)

References 10 publications

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“…Dual rail logic has been identified as an interesting countermeasure against DPA in several works [5][6] [7][10] [11][12] [14] since its associated dual rail encoding theoretically allows reducing the correlation between the processed data and power consumption. However, this claim holds if and only if some conditions are fulfilled [5].…”

Section: Secure Triple Track Logic Conceptsmentioning

confidence: 99%

“…However, this claim holds if and only if some conditions are fulfilled [5]. As highlighted in [5], these conditions are related to the impact of the place and route steps on both the switching currents and the timings of dual rail designs.…”

Section: Secure Triple Track Logic Conceptsmentioning

confidence: 99%

“…Several implantations of robust dual rail cells are available in the literature [5][6] [7][10] [11] [12]. Most of these have been proposed to design robust ASIC, and a few works were dedicated to mapping of secure dual rail logic on FPGA [13].…”

Section: Introductionmentioning

confidence: 99%

“…Among all these works, an investigation of the effective robustness against DPA of dual rail logic has been introduced in [5][14] [15]. These evaluations demonstrated that the load imbalances introduced during place and route steps significantly reduce the robustness against DPA of dual rail logic.…”

Section: Introductionmentioning

confidence: 99%

“…These evaluations demonstrated that the load imbalances introduced during place and route steps significantly reduce the robustness against DPA of dual rail logic. More precisely, the authors of [5] identified the potential mismatches of data propagation delays through different data paths as the main remaining weakness of dual rail logic against DPA. As a result, they suggested in [5] the use of an additional third wire to simultaneously balance the power consumption and the timing, thus obtaining quasi-data independent power consumption and computation time logic.…”

Section: Introductionmentioning

confidence: 99%

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Evaluation on FPGA of triple rail logic robustness against DPA and DEMA

Lomne¹,

Maurine²,

Торрес³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind triple rail logic are valid and may provide interesting design guidelines to get DPA resistant circuits which are also more robust against DEMA.

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Section: Secure Triple Track Logic Conceptsmentioning

confidence: 99%

Section: Secure Triple Track Logic Conceptsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA

Lomne¹,

Maurine²,

Торрес³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

Self Cite

View full text Add to dashboard Cite

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An overview of hardware-level statistical power analysis attack countermeasures

Mayhew

Mureşan

2016

J Cryptogr Eng

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Implementation of a decoupling based power analysis attack countermeasure

Mayhew

Mureşan

2016

IET Circuits, Devices & Systems

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This study presents new prototyped evaluation results for the authors' proposed power analysis attack countermeasure architecture based on decoupling individual sensitive modules with low current consumption. The proposed architecture includes a switch box module to randomise internal connections, mixing residual information that may leak through non-ideal switch elements and uneven charge cycles. The two implementations evaluated are a printed circuit board (PCB) developed using stand-alone CMOS components and the post-layout simulation of a circuit developed in 0.18 µm TSMC CMOS technology using Cadence. Both systems were able to protect a decoupled 8-bit XOR module from a correlation power analysis performed using traces collected at the power supply rail for at least 8000 plaintext inputs. The results show that the countermeasure is suitable for both on-chip and on-board designs. Analysis of the measurements collected from the PCB test system demonstrates the need to balance the charge/ discharge frequency of the decoupling elements against the operational frequency of the decoupled modules. From the layout, an individual decoupling element was found to be similar in size to the decoupled 8-bit XOR module, with all four decoupling elements occupying a total of 51% of the layout area. This percentage is expected to decrease in the context of larger, more complex systems.

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Improvement of dual rail logic as a countermeasure against DPA

Cited by 21 publications

References 10 publications

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA

An overview of hardware-level statistical power analysis attack countermeasures

Implementation of a decoupling based power analysis attack countermeasure

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