Improved analog and RF performances of gate-all-around junctionless MOSFET with drain and source extensions

Djeffal, F.; Ferhati, H.; Bentrcia, Toufik

doi:10.1016/j.spmi.2015.09.041

Cited by 46 publications

(15 citation statements)

References 16 publications

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“…Instead, the intrinsic gain and cutoff frequency were observed to be degraded by the hot carrier effect; a relative degradation of 15.44% for both of the analog parameters was reported [32]. The designer could improve the analog performance (small signal parameters and drain current drivability) by adding source and drain extensions, as shown in Figure 6 [24]. The structure that is depicted in Figure 5 can be further modified in order to increase the device performance.…”

Section: Gate-all-aroundmentioning

confidence: 99%

“…This device turned out to be the first one of a new generation of transistors. In the last decades, many other junctionless devices were proposed, which includes FinFET , Gate-All-Around (GAA) [24][25][26][27][28][29][30][31][32][33][34][35][36][37], Single Gate (SGJLT) [38][39][40][41][42][43][44][45][46][47][48][49][50], Double Gate (DGJLT) , Thin Film (TFT) [76][77][78][79][80][81][82][83][84][85][86], and Tunnel FET (TFET) [87][88][89][90][91][92][93][94][95][96][97]. Because most of the review papers on JLTs were published in 2010-2014…”

Section: Introductionmentioning

confidence: 99%

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Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Section: Gate-all-aroundmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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“…The various short channel effects arise due to parasitic capacitances, drain induced barrier lowering, mobility degradation, hot carrier effects etc. To overcome these effects the devices, need to be engineered using different techniques like gate engineering and channel engineering [2] [ [10][11][12][13][14]. Gate engineering includes changing the material of the gate with different work functions, designing double gate, triple gate and multi-gate structures.…”

Section: Introductionmentioning

confidence: 99%

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

Mendiratta

Tripathi

2021

Silicon

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In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) for low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of the proposed transistor. Different sensitivity parameters of dopingless AJ DG MOSFET such as drain extension, length of gate overlapping and oxide thickness are compared with the AJ DG MOSFET with doped channel region. The ON-state current obtained is 3.80 x 10 −6 A/μm with reduced OFF-state leakage current up to1.37 x 10 −17 A/μm. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) of the device obtained are 59.5 mV/decade and 10.5 mV/V respectively. Temperature analysis of proposed device at various temperature such as 250 K,300 K, 350 K and 400 K shows a small variation in OFF-state current (<15%). Additionally, a p-channel AJ DG MOSFET along with n-channel AJ DG MOSFET are designed and their performance is evaluated for CMOS inverter circuit and 6T SRAM cell. All the design and analysis has been done with a 2D/3D Visual TCAD device simulator.

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“…Nanoscale DG TFETs are believed to face an upward amendment to meet the difficulty of decreasing the huge thermal budget required for the formation of the gated p-i-n diode structure. Moreover, in spite of the actual mature experimental techniques, realizing metallurgical junctions in sub-32 nm nodes is considered extremely difficult [ 13 – 15 ]. For this purpose, the junctionless (JL) design is considered the best approach to avoid the above outlined experimental limitations and achieve significant improvements regarding the transistor manufacturing cost [ 14 – 17 ].…”

Section: Introductionmentioning

confidence: 99%

“…For this purpose, the junctionless (JL) design is considered the best approach to avoid the above outlined experimental limitations and achieve significant improvements regarding the transistor manufacturing cost [ 14 – 17 ]. The JL technology is considered to be cost-effective and allows avoiding the high thermal budget [ 15 – 17 ]. The concept of a gated source is used for the JL technology in order to ensure the band-to-band tunneling effect, while materials with high work function are required to generate the tunnel current.…”

Section: Introductionmentioning

confidence: 99%

The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability

Ferhati¹,

Djeffal²,

Bentrcia³

2018

Beilstein J. Nanotechnol.

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In this paper, a new nanoscale double-gate junctionless tunneling field-effect transistor (DG-JL TFET) based on a Si1− xGex/Si/Ge heterojunction (HJ) structure is proposed to achieve an improved electrical performance. The effect of introducing the Si1− xGex material at the source side on improving the subthreshold behavior of the DG-JL TFET and on suppressing ambipolar conduction is investigated. Moreover, the impact of the Ge mole fraction in the proposed Si1− xGex source region on the electrical figures of merit (FoMs) of the transistor, including the swing factor and the I ON/I OFF ratio is analyzed. It is found that the optimized design with 60 atom % of Ge offers improved switching behavior and enhanced derived current capability at the nanoscale level, with a swing factor of 42 mV/dec and an I ON/I OFF ratio of 115 dB. Further, the scaling capability of the proposed Si1− xGex/Si/Ge DG-HJ-JL TFET structure is investigated and compared to that of a conventional Ge-DG-JL TFET design, where the optimized design exhibits an improved switching behavior at the nanoscale level. These results make the optimized device suitable for designing digital circuit for high-performance nanoelectronic applications.

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Improved analog and RF performances of gate-all-around junctionless MOSFET with drain and source extensions

Cited by 46 publications

References 16 publications

Junctionless Transistors: State-of-the-Art

Junctionless Transistors: State-of-the-Art

18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability

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