Implementation of Para-CORDIC Algorithm and Its Applications in Satellite Communication

Sharma, Shashwat; Ravichandran, P.; Kulkarni, Sunil; Vanitha, M.; Lakshminarsimahan, P.

doi:10.1109/artcom.2009.137

Cited by 9 publications

(5 citation statements)

References 6 publications

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“…For 16-bit DDFS, the SFDR of the proposed architecture is more than 86.85 dBc. As shown in Table 3 , the proposed DDFS is superior to the previous works in terms of SFDR, SNR, output resolution, and tuning latency [ 6 , 17 , 18 , 26 , 27 ]. According to the high performance of the proposed DDFS, it is very suited for medical instruments and body care network systems [ 46 – 49 ].…”

Section: Discussionmentioning

confidence: 91%

Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

Juang

Chen

et al. 2012

Computational and Mathematical Methods in Medicine

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Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline data path has advantages of high data rate, high precision, high performance, and less hardware cost. The design procedure with performance and hardware analysis for optimization has also been given. It is verified by Matlab simulations and then implemented with field programmable gate array (FPGA) by Verilog. The spurious-free dynamic range (SFDR) is over 86.85 dBc, and the signal-to-noise ratio (SNR) is more than 81.12 dB. The scaling-free CORDIC-based architecture is suitable for VLSI implementations for the DDFS applications in terms of hardware cost, power consumption, SNR, and SFDR. The proposed DDFS is very suitable for medical instruments and body care area network systems.

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Section: Discussionmentioning

confidence: 91%

Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

Juang

Chen

et al. 2012

Computational and Mathematical Methods in Medicine

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“…where, σ i ϵ{−2, −1, 0, 1, 2} . Here, we compute K −1 only for first rotations by bottling all possible scale factors in memory [1,24]. From the expression above the σ i 2 will have three values {0, 1, 4}.And so σ i 2 can choose any one of the three values {0, 1, 4} in each iterationi, thereforefor 16-bit precision actually it is required to store 35 possible scale factors in ROM.…”

Section: ) Scale Factormentioning

confidence: 99%

“…In recent years several CORDIC based FFT was proposed for various applications [1,2,3,4,5]. The conventional radix-2 CORDIC algorithm was implemented using word serial and digit pipelined architectures.…”

Section: Introductionmentioning

confidence: 99%

“…a) X/Y path of the system, b) realization of X/Y path is utilised to perform the direction of the vector. The direction of micro rotations in binary form is represented by the variable d' (d − θ) and θ has a linear relationship with negative slope being observed except for someθvalue, called breakpoints[1, 27]. There by computing‗d' from θ using simple addition operation as shown in theFig.…”

mentioning

confidence: 99%

“…becomes unity thereafter.For the present 16-bit implementation,it is adequate to approximate scale factor for the first 5-iterations only. Scale factor approximation is accomplished in parallel with the micro rotations by bottling all possible scale factors in memory[1, 24]. From the expression above theσ i 2 will have three values {0, 1, 4}.And so σ i 2 can choose any one of the three values {0, 1, 4} in each iterationi, thereforefor 16-bit precisionactually it is required to store 35 possible scale factors in ROM.…”

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confidence: 99%

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A New Memory Reduced Radix-4 CORDIC Processor For FFT Operation

A¹

2013

(IOSR-JVSP

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A complex number can be interpreted as a vector in imaginary plane. The vector rotation in the x/y plane can be realized by rotating a vector through a series of elementary angles. These elementary angles are chosen such that the vector rotation through each of them may be approximated easily with a simple shift and add operation, and their algebraic sum approaches the required rotation angle. This can be exercised by CORDIC ('CO-ordinate Rotation Digital Computer) algorithm in rotation mode. In this paper, we have proposed a pipelined architecture new memory less z-path eliminated CORDIC algorithm for FFT computation. Pipelined architecture by pre computation of direction of micro rotation, radix-4 number representation, and the angle generator has been processed in terms of hardware complexity, iteration delay and memory reduction. Comparison of the proposed architecture with the conventional radix-4 architectures is elaborated. The proposed algorithm also exercises an addressing scheme and the associated angle generator logic in order to eliminate the ROM usage for bottling the twiddle factors. It incorporates parallelism and pipe line processing. The latency of the system is n/2 clock cycles. The throughput rate is one valid result per eight clock cycles. Additionally VLSI implementation on Virtex -4 FPGA is done. The implemented design operates at 450.654 MHZ of clock rate with a power consumption of 175.90mW.

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A High-Speed Low-Power Low-Latency Pipelined ROM-Less DDFS

Hatai

Chakrabarti

2011

Communications in Computer and Information Science

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Implementation of Para-CORDIC Algorithm and Its Applications in Satellite Communication

Cited by 9 publications

References 6 publications

Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

A New Memory Reduced Radix-4 CORDIC Processor For FFT Operation

A High-Speed Low-Power Low-Latency Pipelined ROM-Less DDFS

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