Implementation of fault tolerant techniques into FPNNs

Krcma, Martin; Kotásek, Zdenĕk; Lojda, Jakub

doi:10.1109/fpt.2016.7929559

Cited by 1 publication

(1 citation statement)

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“…This work is the first report of an application of DPR-based clocking schemes for neural networks targeting fault tolerance. Various researchers have demonstrated fault tolerance in hardware implementations of neural networks [6]- [8]. Compared to these works, the work proposed in this paper demonstrates higher fault tolerance and the methodology is feasible in the presence of at least one healthy synapse.…”

Section: Introductionmentioning

confidence: 92%

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

Johnson

Liu

Millard

et al. 2017

2017 International Conference on Field Programmable Technology (ICFPT)

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We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. We demonstrate the repair methodology on a spiking neural network implemented on an FPGA. The system maintains effective functional behavior with a loss of up to 99% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with the tuning circuit (repair unit) which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the overall architecture has a minimal impact on power consumption (1.371W ). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

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Section: Introductionmentioning

confidence: 92%