Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET

Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor

“…Higher gm/Ids values are obtained when the devices are OFF (Vth). Electrically doped devices Figure 10 shows drain conductance of proposed device as a function of drain voltage for different structures.The drain ON (ION) and OFF (IOFF) currents as a function of device temperature [30,31]. These findings revealed that the ON drain current increases linearly as temperature rises, whereas the drain OFF current rises exponentially as temperature rises.…”