Impact of CMOS process scaling and SOI on the soft error rates of logic processes

Hareland, S.A.; Maiz, J.; Alavi, M.; Mistry, K.; Walsta, S.; Dai, Changhong

doi:10.1109/vlsit.2001.934953

Cited by 79 publications

(53 citation statements)

References 2 publications

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“…Researchers have shown that in current systems, memory elements are the most vulnerable system component to soft errors [6,16]. Soft error rates for cache memory are projected to increase linearly with cache size for the next several years [7,11].…”

Section: Introductionmentioning

confidence: 99%

Balancing Performance and Reliability in the Memory Hierarchy

Asadi

Sridharan

Tahoori

et al. 2005

IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.

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Section: Introductionmentioning

confidence: 99%

Balancing Performance and Reliability in the Memory Hierarchy

Asadi

Sridharan

Tahoori

et al. 2005

IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.

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“…Due to this features susceptible temporary faults will be increased [1]. In very deep sub-micron technologies due to atmospheric neutrons and alpha particles the device's fieldlevel reliability is severely impacted by single-event upset (SEU) and multi-bit event upset (MBU).…”

Section: Introductionmentioning

confidence: 99%

Multi-Bit Upset Deduction/Correction for Memory Applications

JushwanthXavier¹,

Kantham²

2013

IJAIS

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In electronics memories are the widely used elements. As the transistor size shrinks multiple-bit upset (MCUs) are increasing due to radiation effects in memories. This affects the reliability of memories. Interleaving and built-in current sensors (BICS) have been success in the case of single event upset (SEC). The process is taken one step further by proposing specific error correction codes to protect memories against multiple-bit upsets and to improve yield have been proposed. The method is evaluated using fault injection experiments. The results are compared with known techniques such as Hamming codes. The proposed codes provide a better performance compared to that of the hamming codes in terms of Single Event Upset. In the case of the Multi Bit Upset it provides better coverage in error deduction and correction schemes.

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“…The technology reliability was considered sufficient, and only a few FT techniques, such as error correcting codes (ECC) [2] in memory, were usually used. However, according to [1,3], the technology trends will pose more and more reliability issues in future. This means, in turn, that FT features are required even in PCs.…”

Section: Introductionmentioning

confidence: 99%

Instruction-Level Fault Tolerance Configurability

Borodin

Juurlink

Hamdioui

et al. 2008

J Sign Process Syst Sign Image Video Technol

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Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance (FT) is becoming increasingly important in computing systems. Several schemes have been proposed to enable a user to configure the FT at the application level, thereby enabling the user to trade stronger FT for performance or vice versa. In this paper, we propose supporting instruction-level rather than application-level configurability of FT, since different parts of some applications (e.g., multimedia) can have different reliability requirements. Weak or no FT will be applied to less critical parts, resulting in time and/or resource gains. These gains can be used to apply stronger FT techniques to the more critical parts; hence increasing the overall reliability. The paper shows how some existing FT techniques can be adapted to support instruction-level FT configurability, how a programmer can specify the desired FT level of the instructions, and how the compiler can manage it automatically. A comparison between the existing FT scheme EDDI (which duplicates all instructions) and the proposed approach is performed both at the kernel and at full application levels. The simulation results show that both the performance and the energy consumption are significantly improved (up to 50% at the kernel and up to 16% at full application level), while the fault coverage depends on the application. For the full application (JPEG encoder), our approach is only applied to one kernel in order to avoid increasing the programming effort significantly.

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Impact of CMOS process scaling and SOI on the soft error rates of logic processes

Cited by 79 publications

References 2 publications

Balancing Performance and Reliability in the Memory Hierarchy

Balancing Performance and Reliability in the Memory Hierarchy

Multi-Bit Upset Deduction/Correction for Memory Applications

Instruction-Level Fault Tolerance Configurability

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