IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI

Stuecheli, Jeffrey; Starke, William J.; Irish, James D.; Arimilli, L. B.; Dreps, Daniel; Blaner, B.; Wollbrink, C.; Allison, Brendan Z.

doi:10.1147/jrd.2018.2856978

Cited by 42 publications

(36 citation statements)

References 6 publications

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“…[149] Chip-to-Chip Ultra Path [150], [151] IFIS [33], [152]- [154] PCIe [155] CXL [156], [157] Cache Coh. (CCIX) [158] Gen-Z [159] OpenCAPI [160], [161] ? Capacity & Access BW [179] Memory Store Cube [180] Proc.…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

“…The media/memory controller is moved from the CPU complex to the media module such that Gen-Z can independently support memory transfers across Gen-Z switches and the Gen-Z fabric. (d) Open Coherent Accelerator Processor Interface (OpenCAPI) [160] homogeneously connects devices to a host platform with a common protocol to support coherency with memory, host interrupts, and exchange messages across devices.…”

Section: E: CCIX ® : Cache Coherent Interconnect For Acceleratorsmentioning

confidence: 99%

“…To support a wide range of connections, the Gen-Z interconnect supports variable speeds ranging from 32 GB/s to more than 400 GB/s. The Open Coherent Accelerator Processor Interface (Open-CAPI) [160] (see Fig. 15(c) and (d)) is a host-agnostic standard that defines procedures to coherently connect devices (e.g., hardware accelerator, network controller, memory module, storage controller) with the host platform.…”

Section: F: Generation-z (Gen-z)mentioning

confidence: 99%

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Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.

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Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

Section: E: CCIX ® : Cache Coherent Interconnect For Acceleratorsmentioning

confidence: 99%

Section: F: Generation-z (Gen-z)mentioning

confidence: 99%

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Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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“…Current trends in the industry, however, are pushing for a 1 Architecture has no name, first author's name is shown. simplified accelerator design shifting the complexity on the cores side (i.e., OpenCAPI [59]). SSAM (2018) Lee et al [55] use Pin tool to characterize the architectural behaviors of kNN, which are at the core of similarity search applications.…”

Section: Classification and Evaluationmentioning

confidence: 99%

“…• More quantitative exploration is required for interconnect networks between the near-memory compute units and also between the host and near-memory compute system. The interplay of NMC units with the emerging interconnect standards like GenZ [109], CXL [110], CCIX [111] and OpenCAPI [59] could be vital in improving the performance and energy efficiency of big data workloads running on NMC enabled servers. • At the application level, algorithms need to provide code and data co-location for energy efficient processing.…”

Section: Open Issues and Future Directionsmentioning

confidence: 99%

Near-memory computing: Past, present, and future

Singh

Chelini

Corda

et al. 2019

Microprocessors and Microsystems

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The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory -called nearmemory computing (NMC) -more viable. Processing right at the "home" of data can significantly diminish the data movement problem of data-intensive applications.In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.

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Memory vs. Storage Software and Hardware: The Shifting Landscape

Lofstead

2020

Communications in Computer and Information Science

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IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI

Cited by 42 publications

References 6 publications

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Near-memory computing: Past, present, and future

Memory vs. Storage Software and Hardware: The Shifting Landscape

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