HyperLogLog Sketch Acceleration on FPGA

Kulkarni, Amit; Chiosa, Monica; Preuber, T.B.; Kara, Kaan; Sidler, David; Alonso, Gustavo

doi:10.1109/fpl50879.2020.00019

Cited by 10 publications

(7 citation statements)

References 38 publications

(32 reference statements)

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“…Compared with the RTL-based ones, our HHD outperforms work [19] which only has one PE. Our HLL has similar performance with work [20] as both designs fully utilize the available bandwidth. The BRAM usage per PE of our implementation is significantly reduced because of the avoidance of the data replication in buffers and the reduction can reach up to 32×.…”

Section: B Comparison With State-of-the-art Designs On Uniform Datasetsmentioning

confidence: 91%

Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS

Chen¹,

Tan²,

Chen³

et al. 2021

Preprint

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FPGAs have become emerging computing infrastructures for accelerating applications in datacenters. Meanwhile, high-level synthesis (HLS) tools have been proposed to ease the programming of FPGAs. Even with HLS, irregular data-intensive applications require explicit optimizations, among which multiple processing elements (PEs) with each owning a private BRAM-based buffer are usually adopted to process multiple data per cycle. Data routing, which dynamically dispatches multiple data to designated PEs, avoids data replication in buffers compared to statically assigning data to PEs, hence saving BRAM usage. However, the workload imbalance among PEs vastly diminishes performance when processing skew datasets. In this paper, we propose a skew-oblivious data routing architecture that allocates secondary PEs and schedules them to share the workload of the overloaded PEs at run-time.In addition, we integrate the proposed architecture into a framework called Ditto to minimize the development efforts for applications that require skew handling. We evaluate Ditto on five commonly used applications: histogram building, data partitioning, pagerank, heavy hitter detection and hyperloglog. The results demonstrate that the generated implementations are robust to skew datasets and outperform the stateof-the-art designs in both throughput and BRAM usage efficiency.1 Ditto, a Transform Pokémon, which is able to reconstitute entire cellular structure to change into what it sees.

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Section: B Comparison With State-of-the-art Designs On Uniform Datasetsmentioning

confidence: 91%

Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS

Chen¹,

Tan²,

Chen³

et al. 2021

Preprint

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“…Note that HyperLogLog [24] has higher theoretical accuracy than LogLog, but it is currently not implementable in P4 language due to the computation of harmonic mean. HyperLogLog can also be implemented in CPU-based and FPGA-based programmable data planes [42]. However, the achievable throughput is limited and the adopted language is target-specific, while P4 can be used to program the data plane pipeline of heterogeneous hardware/software targets.…”

Section: Related Workmentioning

confidence: 99%

Tracking Normalized Network Traffic Entropy to Detect DDoS Attacks in P4

Ding

Savi

Siracusa

2022

IEEE Trans. Dependable and Secure Comput.

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Distributed Denial-of-Service (DDoS) attacks represent a persistent threat to modern telecommunications networks: detecting and counteracting them is still a crucial unresolved challenge for network operators. DDoS attack detection is usually carried out in one or more central nodes that collect significant amounts of monitoring data from networking devices, potentially creating issues related to network overload or delay in detection. The dawn of programmable data planes in Software-Defined Networks can help mitigate this issue, opening the door to the detection of DDoS attacks directly in the data plane of the switches. However, the most widely-adopted data plane programming language, namely P4, lacks supporting many arithmetic operations, therefore, some of the advanced network monitoring functionalities needed for DDoS detection cannot be straightforwardly implemented in P4. This work overcomes such a limitation and presents two novel strategies for flow cardinality and for normalized network traffic entropy estimation that only use P4-supported operations and guarantee a low relative error. Additionally, based on these contributions, we propose a DDoS detection strategy relying on variations of the normalized network traffic entropy. Results show that it has comparable or higher detection accuracy than state-of-the-art solutions, yet being simpler and entirely executed in the data plane.

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“…There are several other recent works that analyze and evaluate the performance of sketch algorithms on FPGAs. Kulkarni et al [33] implement HLL and use it to process streams received through a 100 Gbps network. They use the entire FPGA for the HLL design.…”

Section: Related Workmentioning

confidence: 99%

“…We will show that the cardinality estimate by HLL also provides another valuable accuracy indication and the three sketches together can be used to obtain a rather accurate picture of the distribution, size, and nature of the data set or stream. Wile these sketches have been been shown to benefit from hardware acceleration [32,33], SKT is the first system to combine them into a single design and to study the resulting non-trivial resource-accuracy-performance trade-offs.…”

Section: Introductionmentioning

confidence: 99%

SKT

Chiosa

Preußer²,

Alonso

2021

Proc. VLDB Endow.

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Data analysts often need to characterize a data stream as a first step to its further processing. Some of the initial insights to be gained include, e.g., the cardinality of the data set and its frequency distribution. Such information is typically extracted by using sketch algorithms, now widely employed to process very large data sets in manageable space and in a single pass over the data. Often, analysts need more than one parameter to characterize the stream. However, computing multiple sketches becomes expensive even when using high-end CPUs. Exploiting the increasing adoption of hardware accelerators, this paper proposes SKT , an FPGA-based accelerator that can compute several sketches along with basic statistics (average, max, min, etc.) in a single pass over the data. SKT has been designed to characterize a data set by calculating its cardinality, its second frequency moment, and its frequency distribution. The design processes data streams coming either from PCIe or TCP/IP, and it is built to fit emerging cloud service architectures, such as Microsoft's Catapult or Amazon's AQUA. The paper explores the trade-offs of designing sketch algorithms on a spatial architecture and how to combine several sketch algorithms into a single design. The empirical evaluation shows how SKT on an FPGA offers a significant performance gain over high-end, server-class CPUs.

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HyperLogLog Sketch Acceleration on FPGA

Cited by 10 publications

References 38 publications

Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS

Skew-Oblivious Data Routing for Data-Intensive Applications on FPGAs with HLS

Tracking Normalized Network Traffic Entropy to Detect DDoS Attacks in P4

SKT

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