Hybrid Silicon Photonics for Optical Interconnects

Heck, Martijn J. R.; Chen, Hui-Wen; Fang, Alexander W.; Koch, Brian R.; Liang, Di; Park, Hyundai; Sysak, M.N.; Bowers, John E.

doi:10.1109/jstqe.2010.2051798

Cited by 201 publications

(86 citation statements)

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“…This is because tight-packing and miniaturized metal wires lead to severe information latency and higher power consumption (Haurylau et al, 2007). Proposed solutions to overcome this looming interconnect crisis include replacing the long electrical interconnects with optical interconnects (Heck et al, 2011;Vlasov, 2015). Among possible semiconductor material choices for Si-based photonics, Ge is also the most promising candidate for active photonic devices on Si, thanks to its pseudo-direct gap electronic structure and compatibility with CMOS fabrication processes.…”

Section: Ge-based Mos Gate-stack Engineeringmentioning

confidence: 99%

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

et al. 2016

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We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/ SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5-90 nm), the SiO2 thickness (3-4 nm), and the SiGeshell thickness (2-15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5 × 10 11 cm −2 eV −1 and fixed charge densities of 1-5 × 10 11 cm −2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1−xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.

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Section: Ge-based Mos Gate-stack Engineeringmentioning

confidence: 99%

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

et al. 2016

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“…There are 2 flows, 1 f , and 2 f . Flow 1 f is injected from ingress of edge node (2,0) and leaves at Map03;it traverses a tandem of routers (2,…”

Section: Analysis Of Buffer Sharingmentioning

confidence: 99%

“…At router (2,2) R , 1 f and 2 f share the same input buffer. We transform the original network into a fee-forward model as shown in Figure 4.…”

Section: Analysis Of Buffer Sharingmentioning

confidence: 99%

A New Method for Control-plane Congestion Control in Chip-scale Optical Networks

Shi¹,

Li²,

Qi³

et al. 2016

Proceedings of the 2016 3rd International Conference on Materials Engineering, Manufacturing Technology and Control

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Abstract. Recently, various optical networks have been proposed for chip-scale communication on large-scale many-core chips, including optical burst-switching (OBS). The overall throughput of OBS network is dually constrained by congestion and loss in both the data-plane (i.e., burst contention) and the control-plane (i.e., header packet losses). While previous studies mainly focus on maximizing data-plane throughput, little work has been done on the control-plane congestion problem. In chip-scale OBS, massive fine-grained data bursts, stringent transmission delay budget and moderate network operation frequency have actually constrained the electronic header processing capability, leading to serious network congestion. This paper proposes a new approach based on ingress regulation to overcome the control-plane congestion problem. In our scheme, before being injected, every concurrent packet flow is globally regulated and coordinated so that the aggregated flows do not exceed the header processing capacity of routing nodes, leading to the alleviation of control-plane congestion. We use real application traces to evaluate our method. Simulation results validate that the proposed approach can effectively minimize the control-plane congestion and improve system performance in terms of transmission delay and burst loss rate.

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“…Silicon photonics has been widely studied for the applications in optical interconnects [20], optical communications [21], and nonlinear optics [22] in the past decades. However, these applications are facing many challenges.…”

Section: Introductionmentioning

confidence: 99%

Progress on Waveguide-Integrated Graphene Optoelectronics

Wang

Cheng

2018

Advances in Condensed Matter Physics

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Graphene, a single layer of carbon atoms arranged in the form of hexagonal lattice, has many intriguing optical and electrical properties. However, due to the atomic layer thickness, light-matter interactions in the monolayer graphene are naturally weak when the light is normally incident to the material. To overcome this challenge, waveguide-integrated graphene optoelectronic devices have been proposed and demonstrated. In such coplanar configurations, the propagating light in the waveguide can significantly interact with the graphene layer integrated on the surface of the waveguide. The combination of photonic integrated circuits and graphene also enables the development of graphene devices by using silicon photonic technology, which greatly extends the scope of graphene's application. Moreover, the waveguide-integrated graphene devices are fully CMOS-compatible, which makes it possible to achieve low-cost and high-density integration in the future. As a result, the area has been attracting more and more attention in recent years. In this paper, we introduce basic principles and research advances of waveguide-integrated graphene optoelectronics.

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Hybrid Silicon Photonics for Optical Interconnects

Cited by 201 publications

References 50 publications

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

A New Method for Control-plane Congestion Control in Chip-scale Optical Networks

Progress on Waveguide-Integrated Graphene Optoelectronics

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