Hybrid lithography process for nano-scale devices

Pauliac, S.; Landis, S.; Foucher, J.; Thiault, J.; Faynot, O.

doi:10.1016/j.mee.2006.01.240

Cited by 11 publications

(7 citation statements)

References 15 publications

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“…In order to achieve these pattern resolutions on a full wafer, we chose to carry out a hybrid lithography process combining the high resolution of electron beam (e-beam) lithography with the high throughput of optical lithography in order to decrease wafer exposure time. 25 E-beam exposures were performed on a Vistec VB6 UHR and optical lithography on a KrF [248 nm, deep ultraviolet (DUV)] ASML stepper (PAS 5500/300). The NEB-35 negative chemically amplified resist from Sumitomo Chemical was chosen.…”

Section: Lithography Specificationsmentioning

confidence: 99%

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Pauliac-Vaujour

Brianceau

Comboroure

et al. 2013

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Both sub-22 nm architecture design optimization and reliable, low-cost process development represent major challenges toward nanoscale device fabrication. In order to address the second of these two issues, the authors have demonstrated that it is possible to overcome current tool and process lithography limitations using a capped carbon hard mask process, without dramatically increasing device fabrication costs, as only existing tools are used in this process. Starting from 50 nm patterns, 25 nm fully depleted silicon-on-insulator (FDSOI) transistors with good reliability and acceptable electrical behavior are obtained. This patterning solution may be applied to existing lithography processes (dry or immersion ArF lithography) in order to enhance current resolution capabilities. Moreover, the use of a capping layer enables to set free from photoresist thickness limitations, which are becoming increasingly critical for sub-22 nm feature patterning. Indeed, for such dimensions, photoresist thickness generally needs to be lower than 66 nm in order to avoid pattern collapse effects. This trend can lead to serious integration problems especially for the fabrication of thick stack device architectures. Therefore, in addition to improving current lithography processes, our strategy may also be useful for novel lithography processes such as extreme ultraviolet lithography or maskless lithography. The authors have also demonstrated that the capped carbon hard mask process could enable the patterning of sub-11 nm FDSOI gates, with a current best result close to 7 nm, starting from 30 nm photoresist patterns. Note that all etching steps of the process have been performed in the same etching chamber, which is a key point for meeting industrial requirements. These results show that it is possible to bypass tool and process lithography limitations to pattern sub-22 nm devices without dramatically increasing fabrication costs while maintaining lithography throughput. The authors have therefore shown that the capped carbon hard mask process could be a high-performance and low-cost industry-compatible solution for nanoscale device fabrication.

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Section: Lithography Specificationsmentioning

confidence: 99%

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Pauliac-Vaujour

Brianceau

Comboroure

et al. 2013

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…4,5 For this study, experiments were performed with the NEB-35 formulation from Sumitomo Chemical, 6 which exhibits low molecular weight ͑M w = 1500 g / mol͒ and narrow polydispersity ͑PD= 1.1͒. 2͒.…”

Section: A Hybrid Lithographymentioning

confidence: 99%

“…[6][7][8][9][10] The e-beam exposures were achieved on a Gaussian electron beam lithography equipment ͑Leica VB6UHR from Vistec͒ operating at 100 keV allowing to produce a spot size of about 4 nm; DUV exposures were carried out on an ASML stepper with a wavelength of 248 nm. The process should be optimized to get the best e-beam resolution and prevent the occurrence of standing waves generated by optical exposures.…”

Section: A Hybrid Lithographymentioning

confidence: 99%

Sub-30-nm hybrid lithography (electron beam∕deep ultraviolet) and etch process for fully depleted metal oxide semiconductor transistors

Pauliac-Vaujour

Brianceau

Landis

et al. 2007

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inOn the role of Coulomb scattering in hafnium-silicate gated silicon n and p-channel metal-oxide-semiconductorfield-effect-transistors Low frequency noise analysis in Hf O 2 ∕ Si O 2 gate oxide fully depleted silicon on insulator transistors Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics J. Vac. Sci. Technol. B 24, 710 (2006); 10.1116/1.2180256 Sub-100 nm silicon on insulator complimentary metal-oxide semiconductor transistors by deep ultraviolet optical lithography J.

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“…The technique enables complex chip architectures that require metallisation, doping, heating, multi‐etching and parallel exposure for simultaneous chip fabrication. However, the lithography resolution is low [6] and the lead time takes several months. These limitations present an opportunity for a quicker method of optical device development, the results of which could inform the large scale, complex device designs in DUVL that include opto‐electronic control infrastructure.…”

Section: Introductionmentioning

confidence: 99%

Integration of periodic, sub‐wavelength structures in silicon‐on‐insulator photonic device design

D’Mello

Reshef

Bernal

et al. 2020

IET Optoelectronics

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Rapid advances in high‐resolution chip lithography have accelerated nanophotonic device development on the silicon‐on‐insulator (SOI) platform. The ability to create sub‐wavelength features in silicon has attracted research in photonic band and dispersion engineering and consequently made available a wide array of device functionalities. By drawing on recent demonstrations, the authors review how periodic, sub‐wavelength structures are used for passive wave manipulation in SOI device design. The optical response is evaluated for both orthogonal polarisations at the telecom wavelengths of 1310 and 1550 nm. The results offer a versatile toolkit for the integration of these features in conventional nanophotonic device geometries. Notable benefits include a fine control of dispersion, wavelength and polarisation selectivity, and broadband performance.

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Hybrid lithography process for nano-scale devices

Cited by 11 publications

References 15 publications

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Sub-30-nm hybrid lithography (electron beam∕deep ultraviolet) and etch process for fully depleted metal oxide semiconductor transistors

Integration of periodic, sub‐wavelength structures in silicon‐on‐insulator photonic device design

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