HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems

Saint-Jean, Nicolas; Sassatelli, Gilles; Benoit, Pascal; Torres, Lionel; Robert, Michel

doi:10.1109/isvlsi.2007.51

Cited by 20 publications

(18 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other designs make use of multiple FPGAs. H-Scale [19], by Saint-Jean et al, is a multi-FPGA based homogeneous SoC, with RISC processors and an asynchronous NoC. The S-Scale version supports a multi-threaded sequential programming model with dedicated communication primitives handled at runtime by a simple operating system.…”

Section: Related Workmentioning

confidence: 99%

Heracles

Kinsy

Pellauer

Devadas

2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

View full text Add to dashboard Cite

This paper presentsHeracles, an open-source, functional, parameterized, synthesizable multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile research and teaching tool for architectural exploration and hardware-software co-design. The Heracles toolkit comprises the soft hardware (HDL) modules, application compiler, and graphical user interface. It is designed with a high degree of modularity to support fast exploration of future multicore processors of different topologies, routing schemes, processing elements (cores), and memory system organizations. It is a component-based framework with parameterized interfaces and strong emphasis on module reusability. The compiler toolchain is used to map C or C++ based applications onto the processing units. The GUI allows the user to quickly configure and launch a system instance for easy factorial development and evaluation. Hardware modules are implemented in synthesizable Verilog and are FPGA platform independent. The Heracles tool is freely available under the open-source MIT license at: http://projects.csail.mit.edu/heracles.

show abstract

Section: Related Workmentioning

confidence: 99%

Heracles

Kinsy

Pellauer

Devadas

2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

View full text Add to dashboard Cite

show abstract

“…The other 6% cases do not converge to a unique solution but they present oscillations between two or more frequencies for each PE. It is assumed that in these conflictive cases an external mechanism such as task migration [32,33] is used to solve the problem.…”

Section: Convergencementioning

confidence: 99%

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC

Puschini

Clermidy

Benoit

et al. 2008

International Journal of Reconfigurable Computing

Self Cite

View full text Add to dashboard Cite

Recommended by Michael HubnerWith forecasted hundreds of processing elements (PEs), future embedded systems will be able to handle multiple applications with very diverse running constraints. Systems will integrate distributed decision capabilities. In order to control the power and temperature, dynamic voltage frequency scalings (DVFSs) are applied at PE level. At system level, it implies to dynamically manage the different voltage/frequency couples of each tile to obtain a global optimization. This paper introduces a scalable multiobjective approach based on game theory, which adjusts at run-time the frequency of each PE. It aims at reducing the tile temperature while maintaining the synchronization between application tasks. Results show that the proposed run-time algorithm requires an average of 20 calculation cycles to find the solution for a 100-processor platform and reaches equivalent performances when comparing with an offline method. Temperature reductions of about 23% were achieved on a demonstrative test-case.

show abstract

“…In the academic domain, Saint-Jean et al present a framework [6] to develop both hardware and software for an MPSoC platform. In that work, the hardware architecture is based on RISC processors, interconnected by a network-on-chip, where each core has it own memory.…”

Section: Related Workmentioning

confidence: 99%

A virtual platform for multiprocessor real-time embedded systems

Silva

Barcelos

Wagner

et al. 2008

Proceedings of the 6th International Workshop on Java Technologies for Real-Time and Embedded Systems

View full text Add to dashboard Cite

This paper presents a virtual platform for the development and test of application software, low-level software, and hardware components for an MPSoC (Multiprocessor System-on-Chip) platform, where components are interconnected by a network-onchip (NoC). The environment is aimed at the development of multithread real-time embedded applications in Java language. Communication and task management services are provided that are able to deal with real-time restrictions, following the RTSJ standard. SystemC models are used to describe processors and network connections that have equivalent descriptions in VHDL. Performance and power / energy evaluation are made possible, helping to shorten cycles for embedded system development, integration, and test.

show abstract

HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems

Cited by 20 publications

References 5 publications

Heracles

Heracles

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC

A virtual platform for multiprocessor real-time embedded systems

Contact Info

Product

Resources

About