Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

Abstract

This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both "1" and "0" data. The reference bitline bias of 64 Mb chip is designed to keep intermediate value of "1" and "0" data at any operating temperatures from C to 85 C by introducing a modified band-gap reference circuit with 3 bit temperature coefficient trimmers and 6 bit digital-to-analog converter (DAC) using laser fuses. The measured result shows the improvement of tail-to-tail cell signal windows by 22 mV. Moreover, a new reference bias circuit called the "elevator circuit" with 3 bit temperature coefficient trimmers using ferroelectric fuses installed in a 128 Mb chip compensates array operating voltage VAA fluctuation as well as temperature variation. The elevator circuit enables the temperature dependency control at low external VDD of 1.8 V. This improves cell signal window by 40 mV. The elevator circuit also varies reference bitline bias with array operating voltage VAA variation, resulting in improvement of cell signal windows by 44 mV in the range of 1.5 V 0.2 V VAA.

Conformal BaTiO3 Films with High Piezoelectric Coupling through an Optimized Hydrothermal Synthesis

“…Ferroelectric materials have been studied extensively due to their application in energy harvesting, sensor designs, acoustic sonar, and diagnostic devices. − With the minimization of the size of electronics, ferroelectric films with a 3D microstructure have attracted more attention, especially in nonvolatile ferroelectric random access memory (NVFeRAM). − NVFeRAM is an ideal candidate for the next generation of data storage devices due to its fast switching speed, long data storage time, and low energy consumption. Recently, NVFeRAM with megabit storage density has been fabricated at the research level. , However, the megabit capacities of conventional NVFeRAM are still small in comparison to the gigabit (Gb) capacities of flash memories and dynamic random access memory (DRAM). In order to increase the storage density of NVFeRAM, 3D trenched ferroelectric capacitors have been developed via conformal ferroelectric thin film deposition techniques. − This conformal ferroelectric film increases the effective area of the capacitor and the stored charge per unit area of chip, which in turn leads to an increase in storage density of the NVFeRAM.…”

“…Recently, NVFeRAM with megabit storage density has been fabricated at the research level. 9,10 However, the megabit capacities of conventional NVFeRAM are still small in comparison to the gigabit (Gb) capacities of flash memories and dynamic random access memory (DRAM). In order to increase the storage density of NVFeRAM, 3D trenched ferroelectric capacitors have been developed via conformal ferroelectric thin film deposition techniques.…”

Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes

“…In order to overcome the traditional Flash scaling issue, there are two main technical solutions: one is based on the traditional flash, through further reducing the cell size to improve the storage density; the other one is to introduce emerging memory technology, such as magnetoresistive random access memory (MRAM) [ 5 , 6 , 7 , 8 , 9 ], ferroelectric random access memory (FRAM) [ 10 ], phase-change memory (PCM) [ 11 , 12 ], and RRAM [ 13 , 14 , 15 ], etc.…”