1978
DOI: 10.1109/isscc.1978.1155864
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Abstract: IN MOST ANALOG integrated circuits, only a few transistors must withstand large collector-emitter voltage. This fact can be exploited by desiguing the IC process for optimization of the low voltage parts and designing the circuit with a dense linear technique to be describcd. To test this approach; a redesign of an earlier model*, was fabricated using an existing 3.81.1, 0.7Q-cm standard process normally applied for 51' TTL logic. In addition to decreased chip size, ac performance is enhanced due to decreased…

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