High Temperature Characteristics of GaN-Based Inverter Integrated With Enhancement-Mode (E-Mode) MOSFET and Depletion-Mode (D-Mode) HEMT

Xü, Zhe; Wang, Jinyan; Cai, Yong; Liu, Jingqian; Yang, Zhen; Li, Xiaoping; Wang, Maojun; Yu, Min; Xie, Bing; Wu, Wengang; Ma, Xiaohua; Zhang, Jincheng; Hao, Yue

doi:10.1109/led.2013.2291854

Cited by 58 publications

(37 citation statements)

References 8 publications

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“…The width of the transition voltage region (VTR= VIH -VIL) is a way of measure the ambiguity of the logic inverter [14], which must be as low as possible. The transition voltage width was 0.6 V/5 V (12%) in our case, which is smaller than the lowest values in the literature 1 V/5 V (20%) [10] and 1.6 V/7 V (22%) [13]. The low-input-logic noise margin (NML=VIL -VOL) and high-inputlogic noise margin (NMH=VIH -VOH) are 2.13 V/ 2.5V (85.2%) and 2.2 V/2.5 V (88%) respectively, which outperforms the best values of 1.7 V/2.5 V (68%) and 2 V/2.5 V (80%) in [10].…”

Section: Resultscontrasting

confidence: 79%

“…54. The high-level output voltage (VOH) and VOL were 5 V and 0.07 V, respectively, yielding a much larger voltage swing of 4.93 V/5 V (98.6%) compared to the best values in the literature of 4.66 V/5 V (93.2%) [10] and 6.3 V/7 V (90%) [13]. The low-level input voltage (VIL) and high-level input voltage (VIH), defined at dVout/dVin = -1, were 2.2 V and 2.8 V respectively.…”

Section: Resultsmentioning

confidence: 83%

“…Recent research show steady improvements on GaN DCFL [10], however the VOL is still quite high, up to 0.3 V and the maximum voltage swing is 4.66 V, which would lead to high logic losses and safety problems. A very distinct property of GaN compared to Silicon is its high temperature operation, which led to the demonstration of GaN DCFLs operating at high temperatures, up to 375 °C [9], [11], however, it resulted in a much degraded operation compared to room temperature (RT).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Zhu

Matioli

2018

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-finger gate design of E-mode GaN MOSHEMT to increase the logic swing voltage and noise margins, and reduce the transition periods. State-of-the-art NMOS inverter was achieved with logic swing voltage of 4.93 V at a supply voltage of 5 V, low-input noise margin of 2.13 V and high-input noise margin of 2.2 V at room temperature. Excellent high temperature performance, at 300°C, was observed with a logic swing of 4.85 V, low-input noise margin of 1.85 V and highoutput noise margin of 2.2V. In addition, GaN-based NAND and NOR NMOS logic gates are reported for the first time with very good performance. Finally, the logic gates were monolithically integrated with high-voltage E-mode power transistors, which reveals a significant step forward towards monolithic integration of GaN power transistors with gate drivers.

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Section: Resultscontrasting

confidence: 79%

Section: Resultsmentioning

confidence: 83%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Zhu

Matioli

2018

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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“…5(b). Several groups have reported that the gate controllability of AlGaN/GaN MIS-gate HEMTs enhances by reducing the interface-state density after some post-annealing processes after oxide layer deposition [15][16][17][18]. To improve the electrical properties of MIS-gate HEMTs, we carried out the post metallization annealing (PMA) process [19].…”

Section: Electrical Properties Of Recessed-gate Algan/gan Hemts Prmentioning

confidence: 99%

Low-Damage Etching for AlGaN/GaN HEMTs Using Photo-Electrochemical Reactions

Sato

Toguchi

Komatsu

et al. 2019

IEEE Trans. Semicond. Manufact.

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This paper describes our recent efforts to optimize photo-electrochemical (PEC) etching for fabricating recessed-gate aluminum gallium nitride/gallium nitride (AlGaN/GaN) high-electron-mobility transistors (HEMTs). Selecting the proper light wavelength and voltage conditions enabled PEC etching on AlGaN/GaN heterostructures to produce smooth and flat surfaces. Self-termination phenomena observed under optimal PEC condition were useful for precisely controlling the etching depth in the AlGaN layer. Two types of HEMTs, i.e., Schottky-gate and metal-insulator-semiconductor (MIS)-gate, were fabricated. A recessed-gate AlGaN/GaN structure fabricated with PEC etching showed positive threshold voltage, and its variation was very small with a standard deviation of only 0.019 V for the Schottky-gate HEMTs and 0.032 V for the MIS-gate HEMTs. A recessed-gate structure with PEC etching showed better current transport controllability with a small subthreshold-slope than that of planar-gate and dry-etched-gate AlGaN/GaN structures.

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“…Consequently, a high off‐state drain leakage current ( I off ) can be a serious issue for the MOSHEMTs. Post metallization annealing (PMA) has been studied to improve the gate contact with dielectric and also to reduce the fixed charges at the dielectric/semiconductor interface or within the dielectric bulk . Most of these studies mainly focus on the influence of PMA on the threshold voltage of MOSHEMTs.…”

Section: Introductionmentioning

confidence: 99%

Off-state drain leakage reduction by post metallization annealing for Al₂ O₃ /GaN/AlGaN/GaN MOSHEMTs on Si

Jiang

Lü

Liu

et al. 2015

Phys. Status Solidi A

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Impact of post metallization annealing (PMA) on the off‐state drain leakage (Ioff) for Al2O3/GaN/AlGaN/GaN metal‐oxide‐semiconductor high electron mobility transistors (MOSHEMTs) on Si has been investigated. After implementation of PMA at 500 °C for 10 min in N2 ambient, the Ioff can be reduced by three orders of magnitude compared to that without PMA. In consequence, a high on/off current ratio of 108 and a steep subthreshold slope of 71 mV/dec are achieved for the MOSHEMTs. The reduction of Ioff results from the suppression of source‐drain surface leakage through the interface between Al2O3 and GaN. The decrease of accumulation capacitance of the MOS capacitors (MOSCAPs) after 500 °C PMA suggests an oxidation process at the GaN surface during the high temperature annealing, which was confirmed by the increase of oxide layer thickness measured by transmission electron microscopy (TEM), and also the increase of GaO/GaN bond ratio at the Al2O3/GaN interface revealed by X‐ray photoelectron spectroscopy (XPS). These results suggest that the significant reduction of Ioff after 500 °C PMA can be attributed to partial surface oxidation of the GaN cap, which suppresses the conduction path at the Al2O3/GaN interface.

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High Temperature Characteristics of GaN-Based Inverter Integrated With Enhancement-Mode (E-Mode) MOSFET and Depletion-Mode (D-Mode) HEMT

Cited by 58 publications

References 8 publications

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Low-Damage Etching for AlGaN/GaN HEMTs Using Photo-Electrochemical Reactions

Off-state drain leakage reduction by post metallization annealing for Al₂ O₃ /GaN/AlGaN/GaN MOSHEMTs on Si

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High Temperature Characteristics of GaN-Based Inverter Integrated With Enhancement-Mode (E-Mode) MOSFET and Depletion-Mode (D-Mode) HEMT

Cited by 58 publications

References 8 publications

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs

Low-Damage Etching for AlGaN/GaN HEMTs Using Photo-Electrochemical Reactions

Off-state drain leakage reduction by post metallization annealing for Al2 O3 /GaN/AlGaN/GaN MOSHEMTs on Si

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Product

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Off-state drain leakage reduction by post metallization annealing for Al₂ O₃ /GaN/AlGaN/GaN MOSHEMTs on Si