High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor

Abstract

As microprocessor speeds approach 1 GHz and heyond the difficulties of at-speed testing continue to increase. In particular. automated test equipment which iiperates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies helow 100 MHz. This method has been used to successfully characterize the operation of a 1 GHL microprocessor chip. [I ] 0-8186-8436-4/98 $10.00 'c: 1998 IEEE 234 c dat:~ to arid tram llic deuce and i t is dso used as an cxtenial clock input to the HPX2000 rcstcr.

System-on-a-chip test-data compression and decompression architectures based on Golomb codes

“…This allows us to use slower testers without increasing the test application time. The external clock and scan clocks must be synchronized, e.g., using the scheme described in [24], [25], and , where the Golomb code parameter is usually a power of two. This allows the bits of to be generated by the decoder at the frequency of .…”

Variable-length input huffman coding for system-on-a-chip test

“…A particular advantage of methods which use data compression coding schemes is that they are capable of exploiting the ever increasing gap between the on-chip test frequency and the ATE operating frequency. While in the past this gap has been exploited at the cost of multiple ATE channels [35,36], hence increasing the bandwidth requirements, approaches which use data compression coding schemes can leverage the frequency ratio without the penalty of extra ATE channels. This is achieved by moving the serialization of test data from the spatial domain (multiple input channels from the ATE at a low frequency to single scan channel at a high frequency) to the temporal domain (single input channel from the ATE at a low frequency to single scan channel at a high frequency).…”

“…It should be noted that for the decompression of T di f f , a CSR architecture [2,30] is used after the VIHC decoder in Figure 5. This work assumes that the ATE is capable of external clock synchronization [36].…”

Wrapper design for testing IP cores with multiple clock domains

“…Since for at-speed testing, it is not necessary to load/unload test data at the rated frequencies, the shift frequency is used to tradeoff testing time against power dissipation. Unlike [4], we do not speed up the test data load/unload to its functional frequency through serializing/de-serializing technique since this will reduce the tester channel capacity and increase test power. Rather, we load/unload test data from/to the ATE at the speed of the tester frequency f t and distribute it to multiple scan chains at the speed of shift frequency f s using the proposed wrapper architecture.…”