High speed multioutput circuits using adiabatic logic

Jayanthi, D.; Shankar, Ajay; Raghavan, S.; Rajasekar, G.

doi:10.1109/icetets.2016.7603058

Cited by 3 publications

(2 citation statements)

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“…In complementary metaloxide semiconductor (CMOS) circuits, several new approaches are emerging to achieve low power consumption. When timing requirement is not crucial, adiabatic logic is the most outstanding approach amidst the various techniques to lessen the power consumption in CMOS circuits [1]. Adiabatic logic suggests the make use of a trapezoidal power clock that permits charging or discharging at a steady current without current flow.…”

Section: Introductionmentioning

confidence: 99%

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Low power architecture of logic gates using adiabatic techniques

Sanadhya

Sharma

2022

IJEECS

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The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.

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Section: Introductionmentioning

confidence: 99%

“…If the T> RCload then charging the circuit time constant (2RCload) is much smaller than T, since the energy dissipation is small. The dissipation of energy is decreased by decreasing the PMOS transistor on-resistance as the dissipated energy (Eadiabatic) is proportional to R and is given by ( 3) and ( 4) [1].…”

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confidence: 99%