High-Resolution Wideband Phase Shifter With Current Limited Vector-Sum

Qian, Huizhen Jenny; Zhang, Bo; Luo, Xun

doi:10.1109/tcsi.2018.2858017

Cited by 32 publications

(10 citation statements)

References 30 publications

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“…where G m_I± and G m_Q± are the transconductances of the core MOSFETs in in-phase and quadrature paths, respectively. For a conventional phase shifter [32], the transconductances are linear to the control code α (e.g., G m_Q+ = kα and G m_I + = k(2 N − 1 − α) for quadrant 1) for easy control. However, a nonlinearity relationship between phase shifts ϕ and control codes α is obtain, which leads to an intrinsic phase error.…”

Section: B Topology and Operation Principlementioning

confidence: 99%

“…11. Compared to the conventional phase shifter without linearity enhancement technology, i.e., current-DACs are controlled by the phase codes directly [32], the phase linearity versus control codes could be improved and phase error could be decreased by the proposed phase linearity enhancement technology, as shown in Fig. 12.…”

Section: ) Reference Voltage Generatormentioning

confidence: 99%

“…For more information, see https://creativecommons.org/licenses/by/4.0/ 50 load resistors are required in the circuits, which are not easy to be implemented precisely on chip. Meanwhile, high-resolution variable gain amplifiers (VGAs) are utilized to improve the phase resolution for low phase error in vector-sum phase shifters [28]- [32]. However, due to the non-linearity of VGAs, off-chip hardware calibration methods, such as digital pre-distortion (DPD) technology, are needed to decrease the phase error, especially for high-resolution vector-sum phase shifters.…”

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confidence: 99%

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High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology

Zhou

Qian

Luo

2021

IEEE Trans. Circuits Syst. I

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In this paper, a wideband vector-sum phase shifter with phase linearity enhancement technology is proposed to minimize phase error. The digital phase shifter synthesizes the output phases by modulating and summing four quadrature signals. A common-source stage with transformer-based matching network and a quadrature-all-pass filter (QAF) are utilized for the quadrature signals generation within a wideband. Besides, to decrease the influence of parasitics on amplitude and phase error, a resistor-based compensation technology is employed in the QAF implementation. Then, to obtain the 360 • range high resolution phase shifts, the quadrature signals are modulated by four Gilbert-type variable gain amplifiers (VGAs) with digital-controlled current-digital to analog converters (current-DACs). To further minimize phase error, an on-chip phase linearity enhancement loop is utilized. The drain voltages of current-DACs are detected and compared to the presupposed reference voltages generated by the loop. Besides, the compared results are fed back to control the current-DACs to achieve phase linearity enhancement. To verify the mentioned mechanism, a 7-bit digital phase shifter operating at 22-44 GHz with on-chip phase linearity enhancement technology is implemented and fabricated in a 28-nm CMOS technology. Based on the phase linearity enhancement technology, the phase shifter exhibits a RMS amplitude error of 0.36-0.59 dB and RMS phase error of 0.92 •-1.02 • without off-chip digital pre-distortion (DPD) technology. The total DC power consumption including the phase linearity enhancement loops is 35 mW under a 0.9V supply voltage.

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Section: B Topology and Operation Principlementioning

confidence: 99%

Section: ) Reference Voltage Generatormentioning

confidence: 99%

mentioning

confidence: 99%

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High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology

Zhou

Qian

Luo

2021

IEEE Trans. Circuits Syst. I

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“…Various on-chip passive baluns are proposed in [24,25,26,27,28,29,30,31]. In this design, an area-saving and performance improvement transformer balun with center open stub is presented.…”

Section: Input Passive Balunmentioning

confidence: 99%

A 6–18 GHz 6-bit active phase shifter in 0.13-µm SiGe BiCMOS

Luo

Yao

et al. 2019

IEICE Electron. Express

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A 6-bit digitally controlled active phase shifter is implemented in 0.13-µm SiGe BiCMOS process for 6-18 GHz phased-arrays. An input passive balun with center open stub is applied to split the single input to differential and achieve high amplitude/phase balance. A degenerated-Q quadrature all-pass filter (QAF) is used to generate two orthogonal vectors with high I/Q accuracy over a wide bandwidth and a main digital-toanalog convertor (DAC) controls the I/Q amplitude to achieve 6-bit phase resolution. In addition, a calibration DAC is adopted to compensate the amplitude variations and the phase error introduced by balun and QAF. Consequently, high resolution along with low gain/phase error can be achieved. The phase shifter has achieved root mean square (RMS) phase error of <4.36°, and RMS gain error of <1.04 dB for all 6-bit phase states at 6-18 GHz. The power gain ranges from 0.95 dB at 6 GHz to −1.85 dB at 18 GHz. Input 1 dB compression point (IP −1dB) is 5.4-8 dBm at 6-18 GHz for 0°-phase state. The total power consumption is 74.4 mW, and the overall chip size is 1.8 × 1.3 mm 2 .

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“…The main challenge associated with RF phase shifters is the demanded large phase shift range, together with the resulted high loss and power consumption. The state‐of‐the‐art mm‐wave phase shifters can be categorised into the switch‐type [4 ], the reflection‐type [5 ], and the vector‐summing [6 ] phase shifters.…”

Section: Introductionmentioning

confidence: 99%

29‐/35 GHz Dual‐band high‐gain phase shifter with hybrid π‐networks

Wei

Ding²,

Yu³

et al. 2020

Electron. lett.

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This Letter presents a 29‐/35 GHz dual‐band high‐gain hybrid π‐network‐based phase shifter. The hybrid π‐network realised by combining electrical tuning through capacitors and magnetic tuning through transformers extends the phase shift range. Furthermore, the phase shift modules are inserted between the vertically stacking transistors to realise the embedded phase shifting with the minimum loss. The Gm‐stages offer the additional signal gain to offset attenuation from the passive phase shifter. This prototype, fabricated in a 28 nm CMOS process, demonstrates a 360° continuous phase shift range with a maximum gain of 22 dB at 35 GHz, and 240° continuous phase shift range with a maximum gain of 20 dB at 29 GHz. It consumes 26 mW power and 1.25 mm × 0.75 mm chip area.

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High-Resolution Wideband Phase Shifter With Current Limited Vector-Sum

Cited by 32 publications

References 30 publications

High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology

High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology

A 6–18 GHz 6-bit active phase shifter in 0.13-µm SiGe BiCMOS

29‐/35 GHz Dual‐band high‐gain phase shifter with hybrid π‐networks

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