2001
DOI: 10.1007/978-3-7908-1816-1_2
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High-Performance Hardware Design and Implementation of Genetic Algorithms

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Cited by 11 publications
(14 citation statements)
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“…The H/W processor for implementing the S/W simulation should be developed to recognize the pattern during unstable communication status due to noise and also take the measures for it in real-time. [7,8,9] Advanced Engineering Forum Vols. 2-3(a) size=50, Iteration=100 (b) size=70, Iteration=100 (c) size=90, Iteration=100…”
Section: Performance and Results Of The Noise Pattern Recognitionmentioning
confidence: 99%
“…The H/W processor for implementing the S/W simulation should be developed to recognize the pattern during unstable communication status due to noise and also take the measures for it in real-time. [7,8,9] Advanced Engineering Forum Vols. 2-3(a) size=50, Iteration=100 (b) size=70, Iteration=100 (c) size=90, Iteration=100…”
Section: Performance and Results Of The Noise Pattern Recognitionmentioning
confidence: 99%
“…At Hewlett-Packard Laboratories, a high-performance hardware implementation of a genetic algorithm is being designed [64]. A 2200x speed-up over software emulation on a 100MHx workstations was reached.…”
Section: Future Workmentioning
confidence: 99%
“…In [1] and [2], survival-based steady-state GA and Compact Genetic Algorithm are used to reduce sizes of a hardware circuit and memory, respectively.…”
Section: B Generation Model Of Hardware Gamentioning
confidence: 99%
“…In [10], hardware GA called H 3 engine that adopts steady-state GA was implemented. In [1], Barry et al developed hardware circuits for Set Coverage Problem using Steady-state GA. In [2], Aporntewan et al proposed a hardware implementation technique for Compact Genetic Algorithm on FPGAs.…”
Section: Introductionmentioning
confidence: 99%