High-level synthesis under multi-cycle interconnect delay

Abstract

-As process technology goes into deep submicron range, interconnect delay becomes dominant among overall system delay, occupying most of the system clock cycle time. Interconnect delay is now a crucial factor that needs to be considered even during high-level synthesis. In this paper, we propose a concurrent scheduling and binding algorithm that takes interconnect delay into account. We first define our distributed target architecture, which minimizes the effect of interconnect delay on clock cycle time. We no longer assume that interconnect delay between functional units is a part of one clock cycle. Interconnect delay can span over multiple clock cycles. We incorporate the concept of multi-cycle interconnect delay into scheduling and binding process, to reduce the critical path length and therefore the system latency. We show that by introducing interconnect delay, we can obtain latency improvement of up to 54 % and of 37% on the average.

Architecture and Synthesis for On-Chip Multicycle Communication

“…Based on a similar idea, [14] and [15] proposed a distributed-register architecture in the domain of architectural synthesis. In this architecture, registers are distributed so that each functional unit can perform a computation by reading data from the local dedicated registers and also by writing the result into the local registers.…”

“…Data transfers between different functional units are regarded as global communications that may take multiple cycles, which decouple communication and computation. Under this distributed-register architecture, [14] first performs floorplanning to obtain physical information, then does rescheduling and rebinding to reduce the final latency, [15] performs operation binding, placement and postlayout scheduling sequentially, in which the placement is driven by the interclock slack time obtained by an initial scheduling, [29] formulates the placement problem into a linear programming model to eliminate the potential slack time violation, and resource sharing is performed after placement.…”

“…In addition, the RDR microarchitecture has the following advantages over the distributed-register architecture: 3 1) RDR is highly regular, which greatly facilitates the interconnect delay estimation. Note that all of [14], [15], 3 Note that these strengths are associated with high-performance designs. The RDR architecture is not suitable (or necessary) for low-frequency (and lowpower) designs as due to its unnecessary area (and power) overhead.…”

“…A concurrent scheduling and binding algorithm based on a given floorplan is proposed in [14]. It uses the concept of dynamic critical path list-scheduling introduced by [16].…”

“…The functional unit binding is shown beside the DFG node. According to the algorithm in [14], both nodes 3 and 4 will be ready and compete for ALU1 in clock cycle 3. Since they have the same priority (i.e., critical path length), either one of them may be chosen and bound to ALU1.…”