High Density and High Reliability Chain FeRAM with Damage-Robust MOCVD-PZT Capacitor with SrRuO3/IrO2 Top Electrode for 64Mb and Beyond

Hidaka, O.; Ozaki, T.; Kanaya, Haruichi; Kumura, Y.; Shimojo, Y.; Shuto, S.; Yamada, Yuji; Yahashi, K.; Yamaguchi, Koji; Yamazaki, S.; Takashima, D.; Miyakawa, T.; Shiratake, S.; Ohtsuki, Satoshi; Kunishima, I.; Nitayama, A.

doi:10.1109/vlsit.2006.1705249

Cited by 8 publications

(6 citation statements)

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“…The ferroelectric capacitors in our study are squares with side lengths of 100, 150, 200, and 250 µm, scalable down to 0.1 µm 2 (demonstrated in 2006). [ 30 ] Transforming the Bulk Devices into Flexible FeRAM Capacitors : The fl exing approach followed in this work consists of a single extra processing step utilizing a deep reactive ion etching (DRIE). Figure 7 highlights the fl exing process main steps.…”

Section: Methodsmentioning

confidence: 99%

“…This is subject to further optimization as bulk infl exible PZT cells of 0.1 µm 2 has been previously reported. [ 30 ] Furthermore, the better values for fl exible PZT memory cells on platinum foil are fi rst achieved on silicon. The last step in the reported fabrication fl ow was peeling-off the Pt/PZT stack from silicon substrate.…”

Section: Memory Properties Of Transformed Flexible Pzt Feram Capacitorsmentioning

confidence: 99%

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Thin PZT‐Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

Ghoneim

Zidan

Alnassar

et al. 2015

Adv Elect Materials

102

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A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)‐(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational voltages to achieve coercive electric fields, reduces the sol‐gel coating cycles required (i.e., more cost‐effective), and, fabrication wise, is more suitable for further scaling of lateral dimensions to the nano‐scale due to the larger feature size‐to‐depth aspect ratio (critical for ultra‐high density non‐volatile memory applications). Utilizing the inverse proportionality between substrate's thickness and its flexibility, traditional PZT based FeRAM on silicon is transformed through a transfer‐less manufacturable process into a flexible form that matches organic electronics' flexibility while preserving the superior performance of silicon CMOS electronics. Each memory cell in a FeRAM array consists of two main elements; a select/access transistor, and a storage ferroelectric capacitor. Flexible transistors on silicon have already been reported. In this work, we focus on the storage ferroelectric capacitors, and report, for the first time, its performance after transformation into a flexible version, and assess its key memory parameters while bent at 0.5 cm minimum bending radius.

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Section: Methodsmentioning

confidence: 99%

Section: Memory Properties Of Transformed Flexible Pzt Feram Capacitorsmentioning

confidence: 99%

Thin PZT‐Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

Ghoneim

Zidan

Alnassar

et al. 2015

Adv Elect Materials

102

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“…1(a) shows the hysteresis shape of 90 nm-film-thickness MOCVD-PZT ferroelectric capacitor under different temperature conditions. The capacitor is 0.44 m 0.44 m [6]. The hysteresis shape is deformed by temperature variation.…”

Section: Introductionmentioning

confidence: 99%

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

Ogiwara

Takashima

Doumae

et al. 2015

IEEE J. Solid-State Circuits

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This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both "1" and "0" data. The reference bitline bias of 64 Mb chip is designed to keep intermediate value of "1" and "0" data at any operating temperatures from C to 85 C by introducing a modified band-gap reference circuit with 3 bit temperature coefficient trimmers and 6 bit digital-to-analog converter (DAC) using laser fuses. The measured result shows the improvement of tail-to-tail cell signal windows by 22 mV. Moreover, a new reference bias circuit called the "elevator circuit" with 3 bit temperature coefficient trimmers using ferroelectric fuses installed in a 128 Mb chip compensates array operating voltage VAA fluctuation as well as temperature variation. The elevator circuit enables the temperature dependency control at low external VDD of 1.8 V. This improves cell signal window by 40 mV. The elevator circuit also varies reference bitline bias with array operating voltage VAA variation, resulting in improvement of cell signal windows by 44 mV in the range of 1.5 V 0.2 V VAA.

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“…There have been recent demonstrations of high density FRAMs through test chips. [1][2][3][4][5][6][7][8] A 64 Mbit one transistor-one capacitor (1T-1C) FRAM was reported on the 150 nm technology node 1,2) that had a 0.34 mm 2 capacitor-over-bit line (COB) cell, and a 0.25 mm 2 cell at the 130 nm technology node. 3) Using similar SrRuO 3 /IrO 2 top electrode, a chain FRAM 4,5) has been reported for a 0.61 mm 2 cell.…”

Section: Introductionmentioning

confidence: 99%

Manufacturable High-Density 8 Mbit One Transistor–One Capacitor Embedded Ferroelectric Random Access Memory

Udayakumar

Moïse

Summerfelt

et al. 2008

jjap

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Enhanced yield and reliability through process improvements, leading to a manufacturable process for a full-bit functional 8 Mbit one transitor-one capacitor (1T-1C) embedded ferroelectric random access memory (eFRAM) fabricated within a lowleakage 130 nm, 5 lm Cu/fluorosilicate glass (FSG) interconnect complementary metal oxide semiconductor (CMOS) logic process, are described. Higher signal margins are further enabled by the single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements. Retention tests on wafers with signal margins above a threshold value for screen show no bit fails for bakes extending up to 1000 h, suggesting retention lifetimes of more than 10 years at 85 C. Using the qualified process reported in this paper, commercial products are being routinely produced in our fabrication facilities.

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High Density and High Reliability Chain FeRAM with Damage-Robust MOCVD-PZT Capacitor with SrRuO3/IrO2 Top Electrode for 64Mb and Beyond

Cited by 8 publications

References 1 publication

Thin PZT‐Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

Thin PZT‐Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

Manufacturable High-Density 8 Mbit One Transistor–One Capacitor Embedded Ferroelectric Random Access Memory

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