Heterogeneous Integration of BEOL Logic and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and Resistive RAM at a 130 nm node

Srimani, Tathagata; Hills, G.W.; Bishop, Mindy D.; Lau, Christian; Kanhaiya, Pritpal S.; Ho, Rebecca; Amer, Mohamed A.; Chao, Mango C.-T.; Yu, Andrew; Wright, Andrew; Ratkovich, A.; Aguilar, D.; Bramer, A.; Cecman, C.; Chov, A.; Clark, Gregory A.; Michaelson, G.; Johnson, M.; Kelley, Kyle; Manos, Patricia; Mi, Kim Hyun; Suriono, U.; Vuntangboon, S.; Xue, Huijun; Humes, Jefford; Soares, Stênio Sã Rosário Furtado; Jones, Brian L.; Burack, S.; Arvind, .; Chandrakasan, Anantha P.; Ferguson, Bryan W.; Nelson, Matthew D.; Shulaker, Max M.

doi:10.1109/vlsitechnology18217.2020.9265083

Cited by 17 publications

(8 citation statements)

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“…As the gate length is reduced, the impact of source and drain fringe fields decreases the coupling between the gate and the channel, leading to an increase in SS. Assuming L g and in the limit of small V ds , we derive SS from (11) as…”

Section: Short-channel Effectsmentioning

confidence: 99%

“…The electrostatic limitations of bulk 3-D-semiconductors have made low-dimensional (low-D) materials such as carbon nanotubes (CNTs) and 2-D materials promising channel materials for extremely scaled FETs for digital logic applications [6]- [10] because the intrinsically thin channels (∼0.5-2 nm) enable excellent electrostatic control. Moreover, some low-D FETs [e.g., 1-D CNT FETs (CNFETs), 2-D FETs] also enable monolithic 3-D integration, due to the low temperature of fabrication [11], [12], bringing even larger benefits at the system level [13].…”

Section: Introductionmentioning

confidence: 99%

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Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors

Gilardi

Bennett

Yoon

et al. 2022

IEEE Trans. Electron Devices

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Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (<10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source-and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with <5% error in subthreshold slope over a wide range of parameters versus >2× error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions.

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Section: Short-channel Effectsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors

Gilardi

Bennett

Yoon

et al. 2022

IEEE Trans. Electron Devices

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“…Carbon nanotube FET-based M3D process has emerged as an attractive alternative to the silicon-based M3D process [2], [4], [8]- [11]. This is because CNFET can be fabricated at the temperature below 425 • C, which eliminates potential defects of devices and interconnections on previously fabricated tiers [2]. Hence, in a CNT-based M3D IC, on/off currents of CNFET transistors in different tiers are close to each other.…”

Section: Introductionmentioning

confidence: 99%

“…Shulaker et al [12], [14] and Hills et al [13] have demonstrated applications of CNFET-based M3D processes. Srimani et al [2] have demonstrated commercial-grade M3D process design kits (PDKs) and the operation of logic and SRAM.…”

Section: Introductionmentioning

confidence: 99%

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An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors

Kim

Lee

Seo

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This article presents monolithic-3-D (M3D) SRAM arrays using multiple tiers of carbon nanotube (CNT) transistors. The compiler automatically generates single-tier 2-D SRAM subarrays and multitier 3-D SRAM subarrays with different tiers for cells and peripheral logic. Moreover, the compiler can integrate multiple subarrays of different dimensions to generate larger capacity SRAM arrays. The compiler is demonstrated in a commercial-grade M3D process design kit (PDK) with two tiers of carbon nanotube transistors (CNFETs). Simulations show that the M3D CNT SRAM design can improve the properties of memory compared to the 2-D CNT SRAM design. In a 32-kB memory implementation, the M3D design can reduce footprint, latency, and energy by 33%, 10%, and 19%, respectively. The compiler is used to show the feasibility of fine-grain logic and SRAM stacking in M3D technology.

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Beyond-Silicon Computing: Nano-Technologies, Nano-Design, and Nano-Systems

Hills

2022

Emerging Computing: From Devices to Systems

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Heterogeneous Integration of BEOL Logic and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and Resistive RAM at a 130 nm node

Cited by 17 publications

References 0 publications

Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors

Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors

An SRAM Compiler for Monolithic-3-D Integrated Circuit With Carbon Nanotube Transistors

Beyond-Silicon Computing: Nano-Technologies, Nano-Design, and Nano-Systems

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