HCFTL: A Locality-Aware Page-Level Flash Translation Layer

Chen, Hao; Li, Cheng; Lyu, Min; Xu, Yinlong

doi:10.23919/date.2019.8715252

Cited by 11 publications

(6 citation statements)

References 7 publications

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“…A series of demand-based FTLs [9,23,25,50,54,63] have been proposed to alleviate the aforementioned double-read problem by further exploiting the locality characteristics of the workloads. One of the most famous representatives, TPFTL [63] proposes two prefetch schemes including requestlevel prefetch and selective prefetch.…”

Section: Ftl and Address Translationmentioning

confidence: 99%

LearnedFTL: A Learning-based Page-level FTL for Improving Random Reads in Flash-based SSDs

Wang¹,

Lin²,

Wu³

et al. 2023

Preprint

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We present LearnedFTL, which applies learned indexes to on-demand page-level flash translation layer (FTL) designs to improve the random read performance of flash-based solidstate drives (SSDs). The first of its kind, it minimizes the number of double reads induced by address translation in random read accesses. To apply the learned indexes to address translation, LearnedFTL proposes dynamic piece-wise regression to efficiently build learned indexes. LearnedFTL also exploits the unique feature of page relocation in SSD internal garbage collection (GC), and embeds the learned index training in GC, which can minimize additional delay on normal read and write operations. Additionally, LearnedFTL employs a bitmap prediction filter to guarantee the accuracy of learned indexes' predictions. With these designs, LearnedFTL considerably speeds up address translation while reducing the number of flash read accesses caused by the demand-based page-level FTL. Our benchmark-driven experiments on a FEMU-based prototype show that LearnedFTL reduces the 99th percentile tail latency by 4.8×, on average, compared to the state-of-the-art TPFTL scheme.

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Section: Ftl and Address Translationmentioning

confidence: 99%

LearnedFTL: A Learning-based Page-level FTL for Improving Random Reads in Flash-based SSDs

Wang¹,

Lin²,

Wu³

et al. 2023

Preprint

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“…DFTL reduces the RAM overhead of the page mapping table and retains the flexibility of the page-level mapping scheme. However, DFTL also has some problems [17]- [20]. It fails to utilize the spatial locality and hot-cold characteristics of the request.…”

Section: Related Workmentioning

confidence: 99%

“…It also fails to efficiently solve the problem of mapping entry eviction, resulting in a large number of translation pages written back to flash translation blocks. These problems have stimulated the emergence of many improved DFTL algorithms, such as TPFTL [17], CDFTL [18], IRRFTL [19], HCFTL [20]. TPFTL proposes to use a two-level LRU queue to manage the mapping table and adaptively select mapping pre-fetching strategies.…”

Section: Related Workmentioning

confidence: 99%

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An Adaptive Read-Write Partitioning Flash Translation Layer Algorithm

et al. 2019

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The classic demand-based flash translation layer (DFTL) algorithm is well-known since it can solve the contradiction between mapping flexibility and the size of mapping cache by dynamically loading mapping entries. However, DFTL failed to utilize the spatial locality and hot-cold characteristics of the request and had an inefficient mapping entry eviction scheme. This paper proposes an adaptive readwrite partitioning flash translation layer algorithm (ARWFTL). First, the cache mapping table (CMT) is divided into the read CMT and the write CMT. The size of the two can be adaptively adjusted by sensing the characteristics of the upper workload and the read-write latency of the underlying flash page. Second, a priority eviction window is set at the tail of the write CMT to evict the clean mapping entry firstly. When there is no clean mapping entry in the priority eviction window, the tail mapping entry and other mapping entries that belong to the same translation page are clustered to write back into the translation page. Then, other written back mapping entries are set to be clean and the tail mapping entry is evicted. Third, a hot data window is set at the head of the write CMT to recognize the hot and cold data of write requests. Then, the hot and cold data are stored in different data blocks of flash to avoid hot and cold data entanglement and reduce valid page migrations in garbage collection. Experimental results show that, compared with DFTL, ARWFTL can reduce the translation page write counts, the valid page migration counts, the block erase counts, and the average response time by 92.8%, 47.7%, 31.7%, and 31.4%, respectively. In addition, ARWFTL is also superior to the other recent DFTL-based improved algorithms, and even exceeds the pure page-level FTL in some indicators. INDEX TERMS Solid-state drive, flash translation layer, adaptive read-write partition, cache mapping table. MINGBO YAN received the B.E. degree in communication engineering from Hangzhou Dianzi University, China, in 2017, where he is currently pursuing the M.E. degree. His current research interest includes storage system design with solid state drive. XIAOCHONG KONG received the B.E. degree in communication engineering from Hangzhou Dianzi University, China, in 2018, where he is currently pursuing the M.E. degree. His current research interest includes storage system design with solid state drive. XIAORONG XU received the Ph.D. degree in signal and information processing from the Nan

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“…However, growing the in-storage DRAM capacity intrinsically increases the manufacturing cost, resulting in lower competitiveness of the intended products. Due to this limitation, several research groups have explored approaches to reducing the DRAM footprint within storage, including the on-demand caching technique of the address mapping table [3], [4], [14]- [16]. However, these approaches essentially trade-offs the I/O performance for the memory capacity, failing to get the best of both worlds.…”

Section: Introductionmentioning

confidence: 99%

HMB-SSD: Framework for Efficient Exploiting of the Host Memory Buffer in the NVMe SSD

2019

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Host Memory Buffer (HMB) is a highlighted feature of the Non-Volatile Memory Express (NVMe) protocol, which is the state-of-the-art storage interface for emerging storage devices such as Solid-State Drives (SSDs). HMB enables the underlying storage to make use of a portion of host memory for caching their address mapping information and/or user data, so that they can overcome the limited capacity of memory within the storage. This technology opens an opportunity to optimize the I/O performance costeffectively by sharing the ample host memory with the severely resource-constrained device. However, it is challenging to study the HMB-based optimization techniques in the practical system because there is no SSD development platform supporting the HMB feature as well as the commercial SSD products veil their internals, not allowing a custom extension. Motivated by this limitation, this paper presents an HMB-supported SSD development platform called HMB-SSD, which is built by faithfully extending an open-source SSD emulator. HMB-SSD enables to easily integrate and evaluate I/O techniques for the HMB feature in an SSD emulator, which closely mimics the behavior of real devices. We demonstrate the proper operation of our platform and the efficacy of the HMB feature with a case study on write buffering. In our empirical study, the SSD storage achieves a large performance benefit with the HMB-based write buffer, yielding up to 86.2% better performance than that of without it.

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HCFTL: A Locality-Aware Page-Level Flash Translation Layer

Cited by 11 publications

References 7 publications

LearnedFTL: A Learning-based Page-level FTL for Improving Random Reads in Flash-based SSDs

LearnedFTL: A Learning-based Page-level FTL for Improving Random Reads in Flash-based SSDs

An Adaptive Read-Write Partitioning Flash Translation Layer Algorithm

HMB-SSD: Framework for Efficient Exploiting of the Host Memory Buffer in the NVMe SSD

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