Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

Chen, Jienan; Hu, Jianhao; Lee, Shuyang; Sobelman, Gerald E.

doi:10.1109/tvlsi.2014.2304834

Cited by 54 publications

(20 citation statements)

References 11 publications

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“…Cases of pipelined FFT processors can be found in [2] and [3]. A pipelined architecture gives high throughputs, however it requires more equipment assets in the meantime.…”

Section: Existing Systemmentioning

confidence: 99%

Modified Butterfly Structure for Split RadixFFT Processors

Soundharya¹,

Reddy²

2017

Nctet-2k17

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“…Cases of pipelined FFT processors can be found in [2] and [3]. A pipelined architecture gives high throughputs, however it requires more equipment assets in the meantime.…”

Section: Existing Systemmentioning

confidence: 99%

Modified Butterfly Structure for Split RadixFFT Processors

Soundharya¹,

Reddy²

2017

Nctet-2k17

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“…Hundreds of architectures for 128-to 2048-point FFT has been proposed by varying the degree of parallelism and the radix factorization [19] [6]. These implementations are optimized in terms of speed, memory used and hardware logic requirements.…”

Section: Related Workmentioning

confidence: 99%

On the FPGA-Based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study

Tran

Gautier

Casseau

2016

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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“…Many FFT implementations have been reported to follow the concept of addressing schemes. Some have used a non-scalable approach targeted to specific applications [8][9][10][11][12]. Others provide scalable implementations in terms the number of FFT points [13][14][15][16][17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Automated Scalable Address Generation Patterns for 2-Dimensional Folding Schemes in Radix-2 FFT Implementations

2018

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Hardware-based implementations of the Fast Fourier Transform (FFT) are highly regarded as they provide improved performance characteristics with respect to software-based sequential solutions. Due to the high number of operations involved in calculations, most hardware-based FFT approaches completely or partially fold their structure to achieve an efficient use of resources. A folding operation requires a permutation block, which is typically implemented using either permutation logic or address generation. Addressing schemes offer resource-efficient advantages when compared to permutation logic. We propose a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in FFT cores. To support this procedure, we develop a mathematical formulation based on Kronecker products algebra for address sequence generation and data flow pattern in FFT core computations, a well-defined procedure for scaling address generation schemes, and an improved approach in the overall automated generation of FFT cores. We have also performed an analysis and comparison of the proposed hardware design performance with respect to a similar strategy reported in the recent literature in terms of clock latency, performance, and hardware resources. Evaluations were carried on a Xilinx Virtex-7 FPGA (Field Programmable Gate Array) used as implementation target.

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Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

Cited by 54 publications

References 11 publications

Modified Butterfly Structure for Split RadixFFT Processors

Modified Butterfly Structure for Split RadixFFT Processors

On the FPGA-Based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study

Automated Scalable Address Generation Patterns for 2-Dimensional Folding Schemes in Radix-2 FFT Implementations

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