Hardware Acceleration of Approximate Transform Module for the Versatile Video Coding Standard

Abstract

Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. VVC introduces several new coding tools that enable better coding performance compared to the High Efficiency Video Coding (HEVC) standard. The Multiple Transform Selection (MTS) concept, as introduced in VVC, relies on three trigonometrical transforms, and at the encoder side, selects the couple of horizontal and vertical transforms that maximises the Rate-Distortion cost. However, the new Discrete Sine Transform (DST)-VII and Discrete Cosine Transform (DCT)-VIII do not have fast computing algorithms and rely on matrix multiplication, which requires high hardware resources especially for large block sizes. This paper tackles the hardware implementation of an approximation of MTS module. This approximation consists in applying adjustment stages, based on sparse block-band matrices, to a variants of DCT-II family mainly DCT-II and its inverse. Therefore, an efficient 2D hardware implementation of the forward and inverse approximate transform module is proposed. The architecture design includes a pipelined and reconfigurable forward-inverse DCT-II core transform. A unified 2D implementation of 16 and 32-point forward-inverse DCT-II, approximate DST-VII and DCT-VIII is also presented. The synthesis results show that the design is able to sustain 2K and 4K videos at 377 and 94 frames per second, respectively, while using only 18% of Alms, 40% of registers and 34% of Digital Signal Processing (DSP) blocks of the Arria10 SoC platform.

Hardware-friendly DST-VII/DCT-VIII approximations for the Versatile Video Coding Standard

“…In fact, the gain in number of multiplications and additions enabled by the approximate transforms through adjustment matrices is low in the context of the VTM software, which includes other time consuming operations. However, this gain in number of operations as well as in memory usage has a significant impact in the context of hardware implementation on Field-Programmable Gate Array (FPGA) and ASIC platforms with limited logic and memory resources [23], [25].…”

“…The particular symmetry property (red curve) enables to save the memory required to store the adjustment matrix coefficients. Moreover, the specific ordering of the coefficients is more convenient for Single Instruction Multiple Data (SIMD) and hardware implementations [23]. However, this additional constraint decreases the performance of the approximate DST-VII in terms of both orthogonality and error with respect to θ = 5 configuration, illustrated by the blue curve.…”

Modern Video Coding: Methods, Challenges and Systems

“…Supporting many types of transforms also has several consequences related to memory allocation, since temporary results from different residual block candidates need to be stored, processed with different transform types and quantized. Therefore, providing high-performance design under the hardware constraints of the target device is a crucial issue [63].…”

“…Most works that propose hardware solutions for the transform and quantization modules focus on optimizations using techniques to reduce the number of calculations and hardware reuse. Some of these works also employ hardware approximation approaches, such as [63]. The work in [64] employs resource reutilization techniques, because the transforms present very similar operations for different block sizes, so it is possible to share calculations between them.…”

“…In [63], the authors discuss the hardware implementation of an approximated MTS module for the VVC standard. Two solutions are proposed: the first one proposes an unified and pipeline-efficient architecture for direct and inverse DCT-II for block sizes of 4x4, 8x8, 16x16 and 32x32 samples with low computational complexity and logical resource allocation, whereas the second solution presents a 2D implementation of the forward and inverse DST-VII and DCT-VIII transforms with an approximate design through adjustments stages.…”