Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter

Xiong, Botao; Li, Yukun; Li, Sicun; Fan, Sheng; Chang, Yuchun

doi:10.1109/tvlsi.2021.3136229

Cited by 4 publications

(3 citation statements)

References 14 publications

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“…The sine function has periodicity and symmetry, so any input can be transformed into a new input within the interval [0, 0.5]. It can be transformed into Equation (3).…”

Section: Preliminary Range Reductionmentioning

confidence: 99%

“…A large number of intensive floating-point trigonometric functions, exponential and logarithmic operations are usually required in the fields of motor control, noise filtering, digital signal processing, etc. [2][3][4][5][6]. In the field of electric power, trigonometric functions are widely used in the calculation of power quality, complex harmonic processing and phase calculation [7].…”

Section: Introductionmentioning

confidence: 99%

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A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions

Jin

et al. 2023

Electronics

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Transcendental functions are an important part of algorithms in many fields. However, the hardware accelerators available today for transcendental functions typically only support one such function. Hardware accelerators that can support miscellaneous transcendent functions are a waste of hardware resources. In order to solve these problems, this paper proposes a reconfigurable hardware architecture for miscellaneous floating-point transcendental functions. The hardware architecture supports a variety of transcendental functions, including floating-point sine, cosine, arctangent, exponential and logarithmic functions. It adopts the method of a lookup table combined with a polynomial computation and reconfigurable technology to achieve the accuracy of two units of least precision (ulp) with 3.75 KB lookup tables and one core computing module. In addition, the hardware architecture uses retiming technology to realize the different operation times of each function. Experiments show that the hardware accelerators proposed can operate at a maximum frequency of 220 MHz. The full-load power consumption and areas are only 0.923 mW and 1.40×104μm2, which are reduced by 47.99% and 38.91%, respectively, compared with five separate superfunction hardware accelerators.

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“…The sine function has periodicity and symmetry, so any input can be transformed into a new input within the interval [0, 0.5]. It can be transformed into Equation (3).…”

Section: Preliminary Range Reductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions

Jin

et al. 2023

Electronics

View full text Add to dashboard Cite

show abstract

“…For the first issue, the SFP format is revised according to the logarithmic number system 12 so that multiplication can be implemented by addition, which is referred to as the small logarithmic floating point (SLFP) format. In the case of SLFP multiplier, the logarithmic (Log) and Anti‐Log converters are realized by LUT6s and the addition is efficiently performed by the carry chain in the configurable logic block (CLB).…”

Section: Introductionmentioning

confidence: 99%

LUT‐DSP usage trade‐off for re‐configurable convolution acceleration core based on small logarithmic floating point representation

Xiong,

Fan,

et al. 2023

Circuit Theory & Apps

Self Cite

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The challenge in designing the high‐performance field‐programmable gate array (FPGA)‐based convolution accelerator is to take full advantage of the on‐chip computing resources. The reported CNN accelerators always exhaust the on‐chip DSPs and leave other computing resources under‐utilized. Hence, this brief presents a novel convolution acceleration core based on the small logarithmic floating‐point (SLFP) format, which results in three contributions. (1) The SLFP<3,5> multiplier is only implemented with LUT6s and operates at 650 MHz with the aid of the carry chain, which provides sufficient accuracy for most CNNs. In addition, a similar structure can be used to implement a SLFP<3,5> divider. (2) The DSPs in the TWO24 SIMD mode are cascaded to implement a 9‐input adder tree. The sum of the multiples of elements (e.g., , ) is easily obtained by configuring the last DSP in the 9‐input adder tree in the accumulation mode, which can support more kernels (e.g., , ) with a high utilization rate (). (3) The convolution core based on the SLFP format only uses LUT6s and DSPs to achieve 1300 MOPS, 433 MOPS, and 81 MOPS for , , and kernel, respectively. In summary, the proposed convolution accelerator not only balances the resource usage of LUT6s and DSPs but also quantizes most CNN models using several simple scaling operations instead of a computing‐intensive retraining algorithm because the distribution of SLFP numbers is very similar to FP32 numbers.

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CellFlow: Automated Standard Cell Design Flow

Prashanth,

Jonna,

Rao

2023

2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter

Cited by 4 publications

References 14 publications

A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions

A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions

LUT‐DSP usage trade‐off for re‐configurable convolution acceleration core based on small logarithmic floating point representation

CellFlow: Automated Standard Cell Design Flow

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