Graphene transport properties upon exposure to PMMA processing and heat treatments

Abstract

The evolution of grapheneʼs electrical transport properties due to processing with the polymer polymethyl methacrylate (PMMA) and heat are examined in this study. The use of stencil (shadow mask) lithography enables fabrication of graphene devices without the usage of polymers, chemicals or heat, allowing us to measure the evolution of the electrical transport properties during individual processing steps from the initial as-exfoliated to the PMMA-processed graphene. Heating generally promotes the conformation of graphene to SiO2 and is found to play a major role for the electrical properties of graphene while PMMA residues are found to be surprisingly benign. In accordance with this picture, graphene devices with initially high carrier mobility tend to suffer a decrease in carrier mobility, while in contrast an improvement is observed for low carrier mobility devices. We explain this by noting that flakes conforming poorly to the substrate will have a higher carrier mobility which will however be reduced as heat treatment enhance the conformation. We finally show the electrical properties of graphene to be reversible upon heat treatments in air up to 200 °C.

Graphene antidot lattice transport measurements

“…The electron and hole field-effect carrier mobilities as well as the gate bias required to observe a charge-neutrality point (CNP) were determined as a function of temperature (-195°C to 150°C in steps of 25°C); this data is shown in Figure 3 (bottom). The data for each temperature was fitted using a least-squared method [10] to determine the position of the charge-neutrality point and to extract the mobility. All sections of the devices show a low level of doping with all CNPs at a gate-bias of <10 V. The sections with 1 and 5 rows show conductance levels of the same order.…”

“…While BCP lithography has poor control over the position and ordering of the nanopatterning, especially when compared to electron-beam lithography (EBL), EBL based on HSQ negative resist has been observed to limit the mobility due to line edge roughness as widths of order tens of nanometers are approached [9]. For HSQ and BCP resist residues remaining after the removal of the etch mask may impede the electrical properties [10].…”

Defect/oxygen assisted direct write technique for nanopatterning graphene

“…The process of creating the mask, or even the simple contact of the mask with graphene, will in many cases compromise the properties of graphene. [21][22][23][24][25][26] A frequently used inorganic e-beam resist for sub-20 nm features in EBL is hydrogen silsesquioxane (HSQ), which is known for doping graphene and being very difficult to remove. 3,21 The positive resist poly(methyl methacrylate) (PMMA) is used to a much greater extent, but under certain circumstances can lead to the presence of unwanted polymer residues, which are difficult to fully remove, and also electrically dope graphene and ultimately reduce the carrier mobility.…”

“…3,21 The positive resist poly(methyl methacrylate) (PMMA) is used to a much greater extent, but under certain circumstances can lead to the presence of unwanted polymer residues, which are difficult to fully remove, and also electrically dope graphene and ultimately reduce the carrier mobility. [22][23][24]26 Block copolymer lithography typically requires complex optimization of the lithographic process, which still prevents widespread use of such techniques in the graphene community. [27][28][29] Several forms of direct-write techniques that do not require a mask have been proposed.…”

Batch fabrication of nanopatterned graphene devices via nanoimprint lithography

“…Figure 1(c) illustrates how the graphene devices were defined via selective laser ablation, 7 which leaves the electrical properties of graphene unaffected. 13 The above processing steps are designed to minimize contact with solvents/ water as well as to avoid resist residues, which are known to degrade electrical parameters of graphene 14 and which can interfere with the following imprint processing steps. The devices are immediately ready for electrical characterization; these measurements may be used as a quality control step before NIL so that further processing is only implemented on wafers/devices of sufficient quality/homogeneity, as previously defined in Ref.…”