Gigasensors for an Attoscope: Catching Quanta in CMOS

Yamamoto

2022

IEICE Trans. Electron.

In this paper, starting from the algorithm, a performanceand energy-efficient 3D structure or shape of the Tensor Processing Engine (TPE) for CNN acceleration is systematically searched and evaluated. An optimal accelerator's shape maximizes the number of concurrent MAC operations per clock cycle while minimizes the number of redundant operations. The proposed 3D vector-parallel TPE architecture with an optimal shape can be very efficiently used for considerable CNN acceleration. Due to implemented support of inter-block image data independency, it is possible to use multiple of such TPEs for the additional CNN acceleration. Moreover, it is shown that the proposed TPE can also be uniformly used for acceleration of the different CNN models such as VGG, ResNet, YOLO, and SSD. We also demonstrate that our theoretical efficiency analysis is matched with the result of a real implementation for an SSD model to which a state-of-the-art channel pruning technique is applied.

Section: Discussionmentioning

confidence: 99%

In Search of the Performance- and Energy-Efficient CNN Accelerators

Yamamoto

2022

IEICE Trans. Electron.

“…Furthermore, hardware realization of the 2D data alignment is relatively difficult. Nowadays, the advances in the 3D VLSI technology [19], stacked memory [20], [21], and Giga-size sensor arrays [22] with a parallel read-out and embedded logic allow realization of massively parallel array processors with one I/O channel per PE (Processing Element) [23]. These technologies are able to achieve the multidimensional data streams [24] and solve the current I/O bottleneck problems on many core architectures.…”

Section: Introductionmentioning

confidence: 99%

3D-DCT Processor and Its FPGA Implementation

Ikegaki

Miyazaki

IEICE Trans. Inf. & Syst.

2011

SUMMARYConventional array processors randomly access input/coefficient data stored in memory many times during three-dimensional discrete cosine transform (3D-DCT) calculations. This causes a calculation bottleneck. In this paper, a 3D array processor dedicated to 3D-DCT is proposed. The array processor drastically reduces data swapping or replacement during the calculation and thus improves performance. The time complexity of the proposed N × N × N array processor is O(N) for an N 3 -size input data cube, and that of the 3D-DCT sequential calculation is O(N 4 ). A specific I/O architecture, throughput-improved architectures, and more scalable architecture are also discussed in terms of practical implementation. Experimental results of implementation on FPGA (fieldprogrammable gate array) suggest that our architecture provides good performance for real-time 3D-DCT calculations.

“…A frontal plane I/O is highly desired for UHPC, as DRAM speed is still not able to catch up with the processor speed, which is often referred to as "Memory Wall" [2]. The advances in 3D VLSI technology [3], stacked memory [4], macro-electronics [5], and Giga size sensors arrays with parallel read-out [6] make a massively-parallel frontal plane I/O subsystem with a single port per processing element (PE) technically possible [7], so that, the streaming data in the form of 2D and 3D matrices can immediately be made available to the processors. Usually, front-end algorithms for processing multi-dimensional data streams require linear transforms of data, which are based on matrix notation.…”

Section: Introductionmentioning

confidence: 99%

Mesh-of-Tori: A Novel Interconnection Network for Frontal Plane Cellular Processors

Ravankar

2010 First International Conference on Networking and Computing

2010

In this paper we propose a novel "Mesh-of-Tori" cellular interconnection network for scalable and massively parallel array processors with frontal plane I/O. The unit (called " -Cell") in this topology is the smallest double (for 2D case) or triple (for 3D) folded torus, which forms the basic 'tile'. The Cells can be repeated and "fused" to form macro-Cells, or "divided" to form smaller Cells, without destroying the homogeneity of the entire structure, to give a highly scalable and cellular "Mesh-ofTori" topology. The key features of the proposed interconnection network are (1) an excellent up and down scalability due to regularity and modularity, (2) no end-around connections, and (3) capability to map 2D streaming data from frontal plane I/O (stacked layer of sensors) to the processing elements. We also provide solutions for stream data manipulation through frontalplane I/O, on the proposed cellular topology.