Norchip 2010 2010
DOI: 10.1109/norchip.2010.5669477
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Generic partial dynamic reconfiguration controller for fault tolerant designs based on FPGA

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Cited by 19 publications
(13 citation statements)
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“…Straka and his colleagues at University of Brno also work on a fault tolerant framework for SRAM-based FPGAs. Very similar to the already mentioned approaches, a so-called Generic Partial Reconfiguration Controller receives error signals from reconfigurable modules and triggers ondemand scrubbing if required [Straka et al 2010b]. Azambuja et al also use majority voters as failure detection mechanisms and scrub a faulty reconfigurable module only after a failure has been detected [Azambuja et al 2008;Azambuja et al 2009].…”
Section: Methodology Attributesmentioning
confidence: 99%
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“…Straka and his colleagues at University of Brno also work on a fault tolerant framework for SRAM-based FPGAs. Very similar to the already mentioned approaches, a so-called Generic Partial Reconfiguration Controller receives error signals from reconfigurable modules and triggers ondemand scrubbing if required [Straka et al 2010b]. Azambuja et al also use majority voters as failure detection mechanisms and scrub a faulty reconfigurable module only after a failure has been detected [Azambuja et al 2008;Azambuja et al 2009].…”
Section: Methodology Attributesmentioning
confidence: 99%
“…In the course of this research, the design of online failure checkers was first proposed in [Straka et al 2007] and later extended to the overall framework [Straka et al 2010a]. The reconfiguration controller is described in [Straka et al 2010b] and a fault injection system is presented in . Finally, a dependability analysis for the framework is described in ].…”
Section: Reconfigurable Stream Processorsmentioning
confidence: 99%
“…This approach consists in overwriting the memory with its desired contents, and may be applied either periodically, regardless of the presence of errors, or triggered by error detection mechanisms. This can be achieved either through concurrent error detection based on circuit redundancy [6][7][8][9][10][11][12] or through a readback of the configuration memory [13][14][15]. The repair time attainable with straightforward global scrubbing (i.e.…”
Section: Introductionmentioning
confidence: 99%
“…And, as FPGAs grow in terms of logic density, configuration memories grow accordingly. As a result, FPGA-based systems with realtime constraints require specialized repair mechanisms, usually based on partial reconfiguration [6][7][8][9][10][11][12][13][14][15][16].…”
Section: Introductionmentioning
confidence: 99%
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