Generation of Vector Pattterns Through Reseeding of Muetiple-Polynomial Linear Feedback Shift Regist

Hellebrand, Sybille; Tarnick, S.; Rajski, J.; Courtois, B.

doi:10.1109/test.1992.527812

Cited by 131 publications

(69 citation statements)

References 10 publications

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“…According to literature [28], when 2 k − 1 ≥ m, namely the period of LFSR 2 k − 1 is greater than the length of the test cube m, we consider establishing a set of linear equations as constructing a Markov chain (X t ) 1≤t≤s over the state set S = {0, 1, · · · , k}. As shown in Fig.…”

Section: Methods Of Calculating the Optimal Block Lengthmentioning

confidence: 99%

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Tian

Shen

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYLinear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, Xfilling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

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Section: Methods Of Calculating the Optimal Block Lengthmentioning

confidence: 99%

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Tian

Shen

et al. 2016

IEICE Trans. Inf. & Syst.

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“…Several techniques were proposed to improve the encoding efficiency of the basic scheme in [10]. Utilizing multiple-polynomial LFSRs was introduced in [11] and [12]. An LFSR reseeding scheme with variable-length seed was proposed in [13].…”

Section: Related Workmentioning

confidence: 99%

Correlation-Based Rectangular Encoding

Lee

Touba

2010

IEEE Trans. VLSI Syst.

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Abstract-In this paper, a technique is presented for improving the compression achieved with any linear decompressor by adding a small nonlinear decoder that exploits bit-wise and pattern-wise correlations present in test vectors. The proposed nonlinear decoder has a regular and compact structure, and allows continuous-flow decompression. It has a very important feature, which is that its design does not depend on the test data. This simplifies the design flow and allows the decoder to be reused when testing multiple cores on a chip. Experimental results show that combining a linear decompressor with the small nonlinear decoder proposed here significantly improves the overall compression.

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“…Hellebrand, et al [1992], proposed a method for improving the encoding efficiency of LFSR reseeding by using a multiple-polynomial LFSR (MP-LFSR). An MP-LFSR has a programmable feedback function, and hence can implement different feedback polynomials.…”

Section: Previous Workmentioning

confidence: 99%

“…Several techniques for improving the encoding efficiency of the basic LFSR reseeding methodology (originally described in [Könemann 1991]) have been proposed in Hellebrand et al [1992Hellebrand et al [ , 1995aHellebrand et al [ , 1995b, Venkataraman et al [1993], Zacharia [1995], Zacharia et al [1996], and Rajski et al [1998a]. These techniques will be described in detail in Section 2 and compared with the new technique proposed in this article (preliminary results were published in Krishna et al [2001]).…”

Section: Introductionmentioning

confidence: 99%

Achieving high encoding efficiency with partial dynamic LFSR reseeding

Krishna

Jas

Touba

2004

ACM Trans. Des. Autom. Electron. Syst.

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Previous forms of LFSR reseeding have been static (i.e., test application is stopped while each seed is loaded) and have required full reseeding (i.e., the length of the seed is equal to the length of the LFSR). A new form of LFSR reseeding is described here that is dynamic (i.e., the seed is incrementally modified while test application proceeds) and allows partial reseeding (i.e. length of the seed is less than that of the LFSR). In addition to providing better encoding efficiency, partial dynamic LFSR reseeding has a simpler hardware implementation than previous schemes based on multiple-polynomial LFSRs.

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Generation of Vector Pattterns Through Reseeding of Muetiple-Polynomial Linear Feedback Shift Regist

Cited by 131 publications

References 10 publications

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Correlation-Based Rectangular Encoding

Achieving high encoding efficiency with partial dynamic LFSR reseeding

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