Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

Comparative study of dopant-segregated Schottky barrier germanium nanowire transistors

“…The equivalent oxide thickness, T ox = 1 nm, and gate work function engineering is applied to obtain suitable voltage bias. [28][29][30] The gate work function varies from 4.25 to 4.65 eV, with 4.45 eV as default. For low power operation application, the drain voltage, V dd = ¹0.5 V. There are two germanide S/D materials, PtGe and NiGe, involved in the simulation.…”

Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories

“…1,2) As a candidate for the future DRAM cell transistor, the fin field-effect transistor (FinFET) fabricated on a bulk Si wafer is highly attractive because of its excellent gate controllability that enables the suppression of SCE, high current drivability due to large effective channel width and small body bias effect, and stable operation without floating body effects. [3][4][5][6] Large current drivability is strongly demanded for future low-voltage, high-speed DRAMs. On the other hand, large gate-induced drain leakage (GIDL) is one of the problems of the FinFET structure.…”

“…On the other hand, large gate-induced drain leakage (GIDL) is one of the problems of the FinFET structure. 6) The GIDL of the FinFET is relatively large because of its large gate-to-drain overlap area and low threshold voltage (V th ). Gate workfunction engineering, such as an in-situ boron-doped polysilicon gate (p+ poly gate) or negative word-line voltage is mandatory to suppress I off which degrades DRAM retention characteristics.…”