Gate Oxide Reliability Issues of SiC MOSFETs Under Short-Circuit Operation

Nguyen, Thanh-That; Ahmed, Ashraf; Thang, T. V.; Park, Joung‐Hu

doi:10.1109/tpel.2014.2353417

Cited by 186 publications

(70 citation statements)

References 21 publications

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“…As evidenced in some tests, this could entail a permanent reduction in the maximum current capability or damage the device such that it does not turn on anymore (a gate-to-source resistance of tens of ohms was observed). This might be confirmed by the inspection of V GS waveform (Fig.10) during SC test which shows reduction of applied voltage, due to increase of the gate leakage current [4]. A similar effect is also experienced after repetitive stress tests [6].…”

Section: Resultssupporting

confidence: 58%

Short-circuit failure mechanism of SiC power MOSFETs

Romano

Maresca

Riccio

et al. 2015

2015 IEEE 27th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD)

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Failure mechanisms during short-circuit conditions of Silicon Carbide Power MOSFETs are analysed in this work, and a possible theoretical explanation is provided. Insight into the physics involved in such processes was inferred through experimental and numerical analyses. The TCAD structure used for electro-thermal simulations was calibrated to fit the I D -V GS characteristics of a commercial device. Adequate physical effects were considered, such as the presence of charges and traps at the oxide-SiC interface and their effect on threshold voltage and carrier mobility. Experimental evidences were explained by analyzing the numerical results. The high temperature reached during these operating conditions was addressed as the main cause of the device failure. The effect on the leakage current and the activation of a parasitic bipolar transistor are also shown.

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Section: Resultssupporting

confidence: 58%

Short-circuit failure mechanism of SiC power MOSFETs

Romano

Maresca

Riccio

et al. 2015

2015 IEEE 27th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD)

View full text Add to dashboard Cite

show abstract

“…Stage 9: t 8 to t 9 : C ds and C gd are charging with C gs constant, while current remains near the full-load value During this period the gate-source voltage is constant at the Miller voltage. Current at the gate can be equated as (17). (17) Integrating both sides of (17) with respect to time, and approximating the rise in drain voltage as V dc , (18) gives the t 8 to t 9 transition time and (19) gives the loss.…”

Section: Stage 4: T 3 To T 4 : the Device Is Now In The Ohmic Regionmentioning

confidence: 99%

“…Furthermore, it is noted that SiC MOSFET gate drive must be bipolar in order to achieve optimum performance [7][8][9][10]15], with careful design to prevent over-or under-voltage on the gate [15] and to reduce parasitic-induced oscillations [9]. Destruction as a result of unwanted device turn-on is of far greater risk in SiC MOSFETs compared with Si MOSFETs [15,16], while gate oxide reliability has been a challenge to SiC [17,18] with some improvement in gate oxide tolerance to temperature more recently [7].…”

Section: Introductionmentioning

confidence: 99%

LV Converters: Improving Efficiency and EMI Using Si MOSFET MMC and Experimentally Exploring Slowed Switching

Roscoe

Holliday

McNeill

et al. 2018

IEEE J. Emerg. Sel. Topics Power Electron.

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Abstract-Widespread adoption of electric vehicles will require AC power distribution systems to accommodate high penetrations of power electronic loads, placing increasing demands on the power quality of gridconnected converters. Recent developments in devices and circuit topologies have potential to improve the intrinsic power quality of these grid interface inverters, reducing the need for passive filters and associated reactive power consumption. Wide bandgap devices, such as SiC, have recently gained much attention due to their low switching losses facilitating raised PWM frequencies. However the high cost of SiC together with electromagnetic interference (EMI) resulting from very rapid switching transitions necessary to realize low switching losses cause concern. Previous research in Si MOSFET modular multilevel converters (MMC) suggests a high efficiency alternative with potential for lower EMI. Si MOSFET MMC benefits are enhanced with parallel-connected devices and slowed switching, made possible by low effective switching frequency. This paper uses experimental results to explore the impact of parallel connection and slowed switching on Si MOSFET MMC losses, and presents improved Si MOSFET switching loss models to resolve inaccuracies observed with conventional Si MOSFET models. EMI is then compared between SiC and Si MMC using carefully controlled relative measurements of radiated EMI.

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“…The SiC MOSFET is claimed to have long-term reliability issues due to its thin oxide layer [19], [20], which is a major reason for not utilizing it in commercial products. In contrast, the depletion mode JFET does not have the reliability issue like the SiC MOSFET and shows a superior short circuit behavior [21], however its normally-on behavior is the main argument 978-1-4673-7151-3/15/$31.00 c 2015 IEEE for not using it as a direct replacement for Si devices.…”

Section: Introductionmentioning

confidence: 99%