GA-based floorplan-aware topology synthesis of application-specific network-on-chip

A Topology Optimization Method of Application-Specific Network-on-Chip

“…This section presents the experiment setup and discusses the results of our GA technique on three multimedia benchmarks, and then we compare the results with the three-level GA technique in [17,18].…”

“…Our technique employs a two-level GA population to present the router selections and node-router mappings respectively. And the router-router mapping employs a quasi-fully connected structure, while [17,18] uses three-level populations to present the same mappings. Because GA technique always gives the approximate optimal solution, it may get suboptimal router-router mappings.…”

“…The experiment results demonstrate that our GA-base technique is valid to generate minimum power consumption topology. Because for the third level, we use fully-connected mappings, and the shortest path algorithm always can find the shortest routes for communication traces, comparing to [17,18], the minimum energy was save 1.8%. But for runtimes, our 2H-GA has great save of 97.79% on average.…”

“…Different from [17], our technique does not restrict the node to router link number to be less or equal to the maximum router port number. Our GA permits the node-router mapping of a router is greater than the port number.…”

“…The ACG of the three benchmarks are obtained from [14], the edges are denoted with bandwidth requirement in Mb/s. We use the same parameters as [17,18]. The core sizes are 1.5 1.5=2.25 mm 2 .…”